cavium-octeon/executive/cvmx-helper-errata.c

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2008 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 /**
0029  *
0030  * Fixes and workaround for Octeon chip errata. This file
0031  * contains functions called by cvmx-helper to workaround known
0032  * chip errata. For the most part, code doesn't need to call
0033  * these functions directly.
0034  *
0035  */
0036 #include <linux/export.h>
0037
0038 #include <asm/octeon/octeon.h>
0039
0040 #include <asm/octeon/cvmx-helper-jtag.h>
0041
0042 /**
0043  * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
0044  * 1 doesn't work properly. The following code disables 2nd order
0045  * CDR for the specified QLM.
0046  *
0047  * @qlm:    QLM to disable 2nd order CDR for.
0048  */
0049 void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
0050 {
0051     int lane;
0052     cvmx_helper_qlm_jtag_init();
0053     /* We need to load all four lanes of the QLM, a total of 1072 bits */
0054     for (lane = 0; lane < 4; lane++) {
0055         /*
0056          * Each lane has 268 bits. We need to set
0057          * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
0058          * 1. All other bits are zero. Bits go in LSB first,
0059          * so start off with the zeros for bits <63:0>.
0060          */
0061         cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
0062         /* cfg_cdr_incx<67:64>=3 */
0063         cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
0064         /* Zeros for bits <76:68> */
0065         cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
0066         /* cfg_cdr_secord<77>=1 */
0067         cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
0068         /* Zeros for bits <267:78> */
0069         cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
0070     }
0071     cvmx_helper_qlm_jtag_update(qlm);
0072 }
0073 EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);