mips/cavium-octeon/dma-octeon.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>
0007  * Copyright (C) 2000, 2001  Ralf Baechle <ralf@gnu.org>
0008  * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
0009  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
0010  * IP32 changes by Ilya.
0011  * Copyright (C) 2010 Cavium Networks, Inc.
0012  */
0013 #include <linux/dma-direct.h>
0014 #include <linux/memblock.h>
0015 #include <linux/swiotlb.h>
0016 #include <linux/types.h>
0017 #include <linux/init.h>
0018 #include <linux/mm.h>
0019
0020 #include <asm/bootinfo.h>
0021
0022 #include <asm/octeon/octeon.h>
0023
0024 #ifdef CONFIG_PCI
0025 #include <linux/pci.h>
0026 #include <asm/octeon/pci-octeon.h>
0027 #include <asm/octeon/cvmx-npi-defs.h>
0028 #include <asm/octeon/cvmx-pci-defs.h>
0029
0030 struct octeon_dma_map_ops {
0031     dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
0032     phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
0033 };
0034
0035 static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
0036 {
0037     if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
0038         return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
0039     else
0040         return paddr;
0041 }
0042
0043 static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
0044 {
0045     if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
0046         return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
0047     else
0048         return daddr;
0049 }
0050
0051 static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
0052 {
0053     if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
0054         paddr -= 0x400000000ull;
0055     return octeon_hole_phys_to_dma(paddr);
0056 }
0057
0058 static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
0059 {
0060     daddr = octeon_hole_dma_to_phys(daddr);
0061
0062     if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
0063         daddr += 0x400000000ull;
0064
0065     return daddr;
0066 }
0067
0068 static const struct octeon_dma_map_ops octeon_gen1_ops = {
0069     .phys_to_dma    = octeon_gen1_phys_to_dma,
0070     .dma_to_phys    = octeon_gen1_dma_to_phys,
0071 };
0072
0073 static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
0074 {
0075     return octeon_hole_phys_to_dma(paddr);
0076 }
0077
0078 static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
0079 {
0080     return octeon_hole_dma_to_phys(daddr);
0081 }
0082
0083 static const struct octeon_dma_map_ops octeon_gen2_ops = {
0084     .phys_to_dma    = octeon_gen2_phys_to_dma,
0085     .dma_to_phys    = octeon_gen2_dma_to_phys,
0086 };
0087
0088 static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
0089 {
0090     if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
0091         paddr -= 0x400000000ull;
0092
0093     /* Anything in the BAR1 hole or above goes via BAR2 */
0094     if (paddr >= 0xf0000000ull)
0095         paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
0096
0097     return paddr;
0098 }
0099
0100 static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
0101 {
0102     if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
0103         daddr -= OCTEON_BAR2_PCI_ADDRESS;
0104
0105     if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
0106         daddr += 0x400000000ull;
0107     return daddr;
0108 }
0109
0110 static const struct octeon_dma_map_ops octeon_big_ops = {
0111     .phys_to_dma    = octeon_big_phys_to_dma,
0112     .dma_to_phys    = octeon_big_dma_to_phys,
0113 };
0114
0115 static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
0116                        phys_addr_t paddr)
0117 {
0118     if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
0119         paddr -= 0x400000000ull;
0120
0121     /* Anything not in the BAR1 range goes via BAR2 */
0122     if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
0123         paddr = paddr - octeon_bar1_pci_phys;
0124     else
0125         paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
0126
0127     return paddr;
0128 }
0129
0130 static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
0131                         dma_addr_t daddr)
0132 {
0133     if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
0134         daddr -= OCTEON_BAR2_PCI_ADDRESS;
0135     else
0136         daddr += octeon_bar1_pci_phys;
0137
0138     if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
0139         daddr += 0x400000000ull;
0140     return daddr;
0141 }
0142
0143 static const struct octeon_dma_map_ops octeon_small_ops = {
0144     .phys_to_dma    = octeon_small_phys_to_dma,
0145     .dma_to_phys    = octeon_small_dma_to_phys,
0146 };
0147
0148 static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
0149
0150 void __init octeon_pci_dma_init(void)
0151 {
0152     switch (octeon_dma_bar_type) {
0153     case OCTEON_DMA_BAR_TYPE_PCIE:
0154         octeon_pci_dma_ops = &octeon_gen1_ops;
0155         break;
0156     case OCTEON_DMA_BAR_TYPE_PCIE2:
0157         octeon_pci_dma_ops = &octeon_gen2_ops;
0158         break;
0159     case OCTEON_DMA_BAR_TYPE_BIG:
0160         octeon_pci_dma_ops = &octeon_big_ops;
0161         break;
0162     case OCTEON_DMA_BAR_TYPE_SMALL:
0163         octeon_pci_dma_ops = &octeon_small_ops;
0164         break;
0165     default:
0166         BUG();
0167     }
0168 }
0169 #endif /* CONFIG_PCI */
0170
0171 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
0172 {
0173 #ifdef CONFIG_PCI
0174     if (dev && dev_is_pci(dev))
0175         return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
0176 #endif
0177     return paddr;
0178 }
0179
0180 phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
0181 {
0182 #ifdef CONFIG_PCI
0183     if (dev && dev_is_pci(dev))
0184         return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
0185 #endif
0186     return daddr;
0187 }
0188
0189 void __init plat_swiotlb_setup(void)
0190 {
0191     phys_addr_t start, end;
0192     phys_addr_t max_addr;
0193     phys_addr_t addr_size;
0194     size_t swiotlbsize;
0195     u64 i;
0196
0197     max_addr = 0;
0198     addr_size = 0;
0199
0200     for_each_mem_range(i, &start, &end) {
0201         /* These addresses map low for PCI. */
0202         if (start > 0x410000000ull && !OCTEON_IS_OCTEON2())
0203             continue;
0204
0205         addr_size += (end - start);
0206
0207         if (max_addr < end)
0208             max_addr = end;
0209     }
0210
0211     swiotlbsize = PAGE_SIZE;
0212
0213 #ifdef CONFIG_PCI
0214     /*
0215      * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
0216      * size to a maximum of 64MB
0217      */
0218     if (OCTEON_IS_MODEL(OCTEON_CN31XX)
0219         || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
0220         swiotlbsize = addr_size / 4;
0221         if (swiotlbsize > 64 * (1<<20))
0222             swiotlbsize = 64 * (1<<20);
0223     } else if (max_addr > 0xf0000000ul) {
0224         /*
0225          * Otherwise only allocate a big iotlb if there is
0226          * memory past the BAR1 hole.
0227          */
0228         swiotlbsize = 64 * (1<<20);
0229     }
0230 #endif
0231 #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
0232     /* OCTEON II ohci is only 32-bit. */
0233     if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
0234         swiotlbsize = 64 * (1<<20);
0235 #endif
0236
0237     swiotlb_adjust_size(swiotlbsize);
0238     swiotlb_init(true, SWIOTLB_VERBOSE);
0239 }