cavium-octeon/crypto/octeon-crypto.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License. See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
0007  *
0008  * MD5/SHA1/SHA256/SHA512 instruction definitions added by
0009  * Aaro Koskinen <aaro.koskinen@iki.fi>.
0010  *
0011  */
0012 #ifndef __LINUX_OCTEON_CRYPTO_H
0013 #define __LINUX_OCTEON_CRYPTO_H
0014
0015 #include <linux/sched.h>
0016 #include <asm/mipsregs.h>
0017
0018 #define OCTEON_CR_OPCODE_PRIORITY 300
0019
0020 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
0021 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
0022                   unsigned long flags);
0023
0024 /*
0025  * Macros needed to implement MD5/SHA1/SHA256:
0026  */
0027
0028 /*
0029  * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
0030  */
0031 #define write_octeon_64bit_hash_dword(value, index) \
0032 do {                            \
0033     __asm__ __volatile__ (              \
0034     "dmtc2 %[rt],0x0048+" STR(index)        \
0035     :                       \
0036     : [rt] "d" (cpu_to_be64(value)));       \
0037 } while (0)
0038
0039 /*
0040  * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
0041  */
0042 #define read_octeon_64bit_hash_dword(index)     \
0043 ({                          \
0044     __be64 __value;                 \
0045                             \
0046     __asm__ __volatile__ (              \
0047     "dmfc2 %[rt],0x0048+" STR(index)        \
0048     : [rt] "=d" (__value)               \
0049     : );                        \
0050                             \
0051     be64_to_cpu(__value);               \
0052 })
0053
0054 /*
0055  * The index can be 0-6.
0056  */
0057 #define write_octeon_64bit_block_dword(value, index)    \
0058 do {                            \
0059     __asm__ __volatile__ (              \
0060     "dmtc2 %[rt],0x0040+" STR(index)        \
0061     :                       \
0062     : [rt] "d" (cpu_to_be64(value)));       \
0063 } while (0)
0064
0065 /*
0066  * The value is the final block dword (64-bit).
0067  */
0068 #define octeon_md5_start(value)             \
0069 do {                            \
0070     __asm__ __volatile__ (              \
0071     "dmtc2 %[rt],0x4047"                \
0072     :                       \
0073     : [rt] "d" (cpu_to_be64(value)));       \
0074 } while (0)
0075
0076 /*
0077  * The value is the final block dword (64-bit).
0078  */
0079 #define octeon_sha1_start(value)            \
0080 do {                            \
0081     __asm__ __volatile__ (              \
0082     "dmtc2 %[rt],0x4057"                \
0083     :                       \
0084     : [rt] "d" (value));                \
0085 } while (0)
0086
0087 /*
0088  * The value is the final block dword (64-bit).
0089  */
0090 #define octeon_sha256_start(value)          \
0091 do {                            \
0092     __asm__ __volatile__ (              \
0093     "dmtc2 %[rt],0x404f"                \
0094     :                       \
0095     : [rt] "d" (value));                \
0096 } while (0)
0097
0098 /*
0099  * Macros needed to implement SHA512:
0100  */
0101
0102 /*
0103  * The index can be 0-7.
0104  */
0105 #define write_octeon_64bit_hash_sha512(value, index)    \
0106 do {                            \
0107     __asm__ __volatile__ (              \
0108     "dmtc2 %[rt],0x0250+" STR(index)        \
0109     :                       \
0110     : [rt] "d" (value));                \
0111 } while (0)
0112
0113 /*
0114  * The index can be 0-7.
0115  */
0116 #define read_octeon_64bit_hash_sha512(index)        \
0117 ({                          \
0118     u64 __value;                    \
0119                             \
0120     __asm__ __volatile__ (              \
0121     "dmfc2 %[rt],0x0250+" STR(index)        \
0122     : [rt] "=d" (__value)               \
0123     : );                        \
0124                             \
0125     __value;                    \
0126 })
0127
0128 /*
0129  * The index can be 0-14.
0130  */
0131 #define write_octeon_64bit_block_sha512(value, index)   \
0132 do {                            \
0133     __asm__ __volatile__ (              \
0134     "dmtc2 %[rt],0x0240+" STR(index)        \
0135     :                       \
0136     : [rt] "d" (value));                \
0137 } while (0)
0138
0139 /*
0140  * The value is the final block word (64-bit).
0141  */
0142 #define octeon_sha512_start(value)          \
0143 do {                            \
0144     __asm__ __volatile__ (              \
0145     "dmtc2 %[rt],0x424f"                \
0146     :                       \
0147     : [rt] "d" (value));                \
0148 } while (0)
0149
0150 /*
0151  * The value is the final block dword (64-bit).
0152  */
0153 #define octeon_sha1_start(value)            \
0154 do {                            \
0155     __asm__ __volatile__ (              \
0156     "dmtc2 %[rt],0x4057"                \
0157     :                       \
0158     : [rt] "d" (value));                \
0159 } while (0)
0160
0161 /*
0162  * The value is the final block dword (64-bit).
0163  */
0164 #define octeon_sha256_start(value)          \
0165 do {                            \
0166     __asm__ __volatile__ (              \
0167     "dmtc2 %[rt],0x404f"                \
0168     :                       \
0169     : [rt] "d" (value));                \
0170 } while (0)
0171
0172 /*
0173  * Macros needed to implement SHA512:
0174  */
0175
0176 /*
0177  * The index can be 0-7.
0178  */
0179 #define write_octeon_64bit_hash_sha512(value, index)    \
0180 do {                            \
0181     __asm__ __volatile__ (              \
0182     "dmtc2 %[rt],0x0250+" STR(index)        \
0183     :                       \
0184     : [rt] "d" (value));                \
0185 } while (0)
0186
0187 /*
0188  * The index can be 0-7.
0189  */
0190 #define read_octeon_64bit_hash_sha512(index)        \
0191 ({                          \
0192     u64 __value;                    \
0193                             \
0194     __asm__ __volatile__ (              \
0195     "dmfc2 %[rt],0x0250+" STR(index)        \
0196     : [rt] "=d" (__value)               \
0197     : );                        \
0198                             \
0199     __value;                    \
0200 })
0201
0202 /*
0203  * The index can be 0-14.
0204  */
0205 #define write_octeon_64bit_block_sha512(value, index)   \
0206 do {                            \
0207     __asm__ __volatile__ (              \
0208     "dmtc2 %[rt],0x0240+" STR(index)        \
0209     :                       \
0210     : [rt] "d" (value));                \
0211 } while (0)
0212
0213 /*
0214  * The value is the final block word (64-bit).
0215  */
0216 #define octeon_sha512_start(value)          \
0217 do {                            \
0218     __asm__ __volatile__ (              \
0219     "dmtc2 %[rt],0x424f"                \
0220     :                       \
0221     : [rt] "d" (value));                \
0222 } while (0)
0223
0224 #endif /* __LINUX_OCTEON_CRYPTO_H */