0001 # SPDX-License-Identifier: GPL-2.0
0002 if CPU_CAVIUM_OCTEON
0003
0004 config CAVIUM_CN63XXP1
0005 bool "Enable CN63XXP1 errata workarounds"
0006 default "n"
0007 help
0008 The CN63XXP1 chip requires build time workarounds to
0009 function reliably, select this option to enable them. These
0010 workarounds will cause a slight decrease in performance on
0011 non-CN63XXP1 hardware, so it is recommended to select "n"
0012 unless it is known the workarounds are needed.
0013
0014 config CAVIUM_OCTEON_CVMSEG_SIZE
0015 int "Number of L1 cache lines reserved for CVMSEG memory"
0016 range 0 54
0017 default 1
0018 help
0019 CVMSEG LM is a segment that accesses portions of the dcache as a
0020 local memory; the larger CVMSEG is, the smaller the cache is.
0021 This selects the size of CVMSEG LM, which is in cache blocks. The
0022 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
0023 between zero and 6192 bytes).
0024
0025 endif # CPU_CAVIUM_OCTEON
0026
0027 if CAVIUM_OCTEON_SOC
0028
0029 config CAVIUM_OCTEON_LOCK_L2
0030 bool "Lock often used kernel code in the L2"
0031 default "y"
0032 help
0033 Enable locking parts of the kernel into the L2 cache.
0034
0035 config CAVIUM_OCTEON_LOCK_L2_TLB
0036 bool "Lock the TLB handler in L2"
0037 depends on CAVIUM_OCTEON_LOCK_L2
0038 default "y"
0039 help
0040 Lock the low level TLB fast path into L2.
0041
0042 config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
0043 bool "Lock the exception handler in L2"
0044 depends on CAVIUM_OCTEON_LOCK_L2
0045 default "y"
0046 help
0047 Lock the low level exception handler into L2.
0048
0049 config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
0050 bool "Lock the interrupt handler in L2"
0051 depends on CAVIUM_OCTEON_LOCK_L2
0052 default "y"
0053 help
0054 Lock the low level interrupt handler into L2.
0055
0056 config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
0057 bool "Lock the 2nd level interrupt handler in L2"
0058 depends on CAVIUM_OCTEON_LOCK_L2
0059 default "y"
0060 help
0061 Lock the 2nd level interrupt handler in L2.
0062
0063 config CAVIUM_OCTEON_LOCK_L2_MEMCPY
0064 bool "Lock memcpy() in L2"
0065 depends on CAVIUM_OCTEON_LOCK_L2
0066 default "y"
0067 help
0068 Lock the kernel's implementation of memcpy() into L2.
0069
0070 config CAVIUM_RESERVE32
0071 int "Memory to reserve for user processes shared region (MB)"
0072 range 0 1536
0073 default "0"
0074 help
0075 Reserve a shared memory region for user processes to use for hardware
0076 memory buffers. This is required for 32bit applications to be able to
0077 send and receive packets directly. Applications access this memory by
0078 memory mapping /dev/mem for the addresses in /proc/octeon_info. For
0079 optimal performance with HugeTLBs, keep this size an even number of
0080 megabytes.
0081
0082 config OCTEON_ILM
0083 tristate "Module to measure interrupt latency using Octeon CIU Timer"
0084 help
0085 This driver is a module to measure interrupt latency using the
0086 the CIU Timers on Octeon.
0087
0088 To compile this driver as a module, choose M here. The module
0089 will be called octeon-ilm
0090
0091 endif # CAVIUM_OCTEON_SOC
