0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 #include <dt-bindings/interrupt-controller/mips-gic.h>
0003 #include <dt-bindings/gpio/gpio.h>
0004 #include <dt-bindings/clock/mt7621-clk.h>
0005 #include <dt-bindings/reset/mt7621-reset.h>
0006
0007 / {
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 compatible = "mediatek,mt7621-soc";
0011
0012 cpus {
0013 #address-cells = <1>;
0014 #size-cells = <0>;
0015
0016 cpu@0 {
0017 device_type = "cpu";
0018 compatible = "mips,mips1004Kc";
0019 reg = <0>;
0020 };
0021
0022 cpu@1 {
0023 device_type = "cpu";
0024 compatible = "mips,mips1004Kc";
0025 reg = <1>;
0026 };
0027 };
0028
0029 cpuintc: cpuintc {
0030 #address-cells = <0>;
0031 #interrupt-cells = <1>;
0032 interrupt-controller;
0033 compatible = "mti,cpu-interrupt-controller";
0034 };
0035
0036 aliases {
0037 serial0 = &uartlite;
0038 };
0039
0040
0041 mmc_fixed_3v3: regulator-3v3 {
0042 compatible = "regulator-fixed";
0043 regulator-name = "mmc_power";
0044 regulator-min-microvolt = <3300000>;
0045 regulator-max-microvolt = <3300000>;
0046 enable-active-high;
0047 regulator-always-on;
0048 };
0049
0050 mmc_fixed_1v8_io: regulator-1v8 {
0051 compatible = "regulator-fixed";
0052 regulator-name = "mmc_io";
0053 regulator-min-microvolt = <1800000>;
0054 regulator-max-microvolt = <1800000>;
0055 enable-active-high;
0056 regulator-always-on;
0057 };
0058
0059 palmbus: palmbus@1e000000 {
0060 compatible = "palmbus";
0061 reg = <0x1e000000 0x100000>;
0062 ranges = <0x0 0x1e000000 0x0fffff>;
0063
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066
0067 sysc: syscon@0 {
0068 compatible = "mediatek,mt7621-sysc", "syscon";
0069 reg = <0x0 0x100>;
0070 #clock-cells = <1>;
0071 #reset-cells = <1>;
0072 ralink,memctl = <&memc>;
0073 clock-output-names = "xtal", "cpu", "bus",
0074 "50m", "125m", "150m",
0075 "250m", "270m";
0076 };
0077
0078 wdt: wdt@100 {
0079 compatible = "mediatek,mt7621-wdt";
0080 reg = <0x100 0x100>;
0081 };
0082
0083 gpio: gpio@600 {
0084 #gpio-cells = <2>;
0085 #interrupt-cells = <2>;
0086 compatible = "mediatek,mt7621-gpio";
0087 gpio-controller;
0088 gpio-ranges = <&pinctrl 0 0 95>;
0089 interrupt-controller;
0090 reg = <0x600 0x100>;
0091 interrupt-parent = <&gic>;
0092 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
0093 };
0094
0095 i2c: i2c@900 {
0096 compatible = "mediatek,mt7621-i2c";
0097 reg = <0x900 0x100>;
0098
0099 clocks = <&sysc MT7621_CLK_I2C>;
0100 clock-names = "i2c";
0101 resets = <&sysc MT7621_RST_I2C>;
0102 reset-names = "i2c";
0103
0104 #address-cells = <1>;
0105 #size-cells = <0>;
0106
0107 status = "disabled";
0108
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&i2c_pins>;
0111 };
0112
0113 memc: syscon@5000 {
0114 compatible = "mediatek,mt7621-memc", "syscon";
0115 reg = <0x5000 0x1000>;
0116 };
0117
0118 uartlite: uartlite@c00 {
0119 compatible = "ns16550a";
0120 reg = <0xc00 0x100>;
0121
0122 clocks = <&sysc MT7621_CLK_UART1>;
0123 clock-names = "uart1";
0124
0125 interrupt-parent = <&gic>;
0126 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
0127
0128 reg-shift = <2>;
0129 reg-io-width = <4>;
0130 no-loopback-test;
0131 };
0132
0133 spi0: spi@b00 {
0134 status = "disabled";
0135
0136 compatible = "ralink,mt7621-spi";
0137 reg = <0xb00 0x100>;
0138
0139 clocks = <&sysc MT7621_CLK_SPI>;
0140 clock-names = "spi";
0141
0142 resets = <&sysc MT7621_RST_SPI>;
0143 reset-names = "spi";
0144
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&spi_pins>;
0150 };
0151 };
0152
0153 pinctrl: pinctrl {
0154 compatible = "ralink,mt7621-pinctrl";
0155
0156 i2c_pins: i2c0-pins {
0157 pinmux {
0158 groups = "i2c";
0159 function = "i2c";
0160 };
0161 };
0162
0163 spi_pins: spi0-pins {
0164 pinmux {
0165 groups = "spi";
0166 function = "spi";
0167 };
0168 };
0169
0170 uart1_pins: uart1-pins {
0171 pinmux {
0172 groups = "uart1";
0173 function = "uart1";
0174 };
0175 };
0176
0177 uart2_pins: uart2-pins {
0178 pinmux {
0179 groups = "uart2";
0180 function = "uart2";
0181 };
0182 };
0183
0184 uart3_pins: uart3-pins {
0185 pinmux {
0186 groups = "uart3";
0187 function = "uart3";
0188 };
0189 };
0190
0191 rgmii1_pins: rgmii1-pins {
0192 pinmux {
0193 groups = "rgmii1";
0194 function = "rgmii1";
0195 };
0196 };
0197
0198 rgmii2_pins: rgmii2-pins {
0199 pinmux {
0200 groups = "rgmii2";
0201 function = "rgmii2";
0202 };
0203 };
0204
0205 mdio_pins: mdio0-pins {
0206 pinmux {
0207 groups = "mdio";
0208 function = "mdio";
0209 };
0210 };
0211
0212 pcie_pins: pcie0-pins {
0213 pinmux {
0214 groups = "pcie";
0215 function = "gpio";
0216 };
0217 };
0218
0219 nand_pins: nand0-pins {
0220 spi-pinmux {
0221 groups = "spi";
0222 function = "nand1";
0223 };
0224
0225 sdhci-pinmux {
0226 groups = "sdhci";
0227 function = "nand2";
0228 };
0229 };
0230
0231 sdhci_pins: sdhci0-pins {
0232 pinmux {
0233 groups = "sdhci";
0234 function = "sdhci";
0235 };
0236 };
0237 };
0238
0239 sdhci: sdhci@1e130000 {
0240 status = "disabled";
0241
0242 compatible = "mediatek,mt7620-mmc";
0243 reg = <0x1e130000 0x4000>;
0244
0245 bus-width = <4>;
0246 max-frequency = <48000000>;
0247 cap-sd-highspeed;
0248 cap-mmc-highspeed;
0249 vmmc-supply = <&mmc_fixed_3v3>;
0250 vqmmc-supply = <&mmc_fixed_1v8_io>;
0251 disable-wp;
0252
0253 pinctrl-names = "default", "state_uhs";
0254 pinctrl-0 = <&sdhci_pins>;
0255 pinctrl-1 = <&sdhci_pins>;
0256
0257 clocks = <&sysc MT7621_CLK_SHXC>,
0258 <&sysc MT7621_CLK_50M>;
0259 clock-names = "source", "hclk";
0260
0261 interrupt-parent = <&gic>;
0262 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
0263 };
0264
0265 xhci: xhci@1e1c0000 {
0266 compatible = "mediatek,mt8173-xhci";
0267 reg = <0x1e1c0000 0x1000
0268 0x1e1d0700 0x0100>;
0269 reg-names = "mac", "ippc";
0270
0271 clocks = <&sysc MT7621_CLK_XTAL>;
0272 clock-names = "sys_ck";
0273
0274 interrupt-parent = <&gic>;
0275 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
0276 };
0277
0278 gic: interrupt-controller@1fbc0000 {
0279 compatible = "mti,gic";
0280 reg = <0x1fbc0000 0x2000>;
0281
0282 interrupt-controller;
0283 #interrupt-cells = <3>;
0284
0285 mti,reserved-cpu-vectors = <7>;
0286
0287 timer {
0288 compatible = "mti,gic-timer";
0289 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
0290 clocks = <&sysc MT7621_CLK_CPU>;
0291 };
0292 };
0293
0294 cpc: cpc@1fbf0000 {
0295 compatible = "mti,mips-cpc";
0296 reg = <0x1fbf0000 0x8000>;
0297 };
0298
0299 cdmm: cdmm@1fbf8000 {
0300 compatible = "mti,mips-cdmm";
0301 reg = <0x1fbf8000 0x8000>;
0302 };
0303
0304 ethernet: ethernet@1e100000 {
0305 compatible = "mediatek,mt7621-eth";
0306 reg = <0x1e100000 0x10000>;
0307
0308 clocks = <&sysc MT7621_CLK_FE>,
0309 <&sysc MT7621_CLK_ETH>;
0310 clock-names = "fe", "ethif";
0311
0312 #address-cells = <1>;
0313 #size-cells = <0>;
0314
0315 resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
0316 reset-names = "fe", "eth";
0317
0318 interrupt-parent = <&gic>;
0319 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
0320
0321 mediatek,ethsys = <&sysc>;
0322
0323 pinctrl-names = "default";
0324 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
0325
0326 gmac0: mac@0 {
0327 compatible = "mediatek,eth-mac";
0328 reg = <0>;
0329 phy-mode = "trgmii";
0330
0331 fixed-link {
0332 speed = <1000>;
0333 full-duplex;
0334 pause;
0335 };
0336 };
0337
0338 gmac1: mac@1 {
0339 compatible = "mediatek,eth-mac";
0340 reg = <1>;
0341 status = "off";
0342 phy-mode = "rgmii-rxid";
0343 };
0344
0345 mdio: mdio-bus {
0346 #address-cells = <1>;
0347 #size-cells = <0>;
0348
0349 switch0: switch0@0 {
0350 compatible = "mediatek,mt7621";
0351 reg = <0>;
0352 mediatek,mcm;
0353 resets = <&sysc MT7621_RST_MCM>;
0354 reset-names = "mcm";
0355 interrupt-controller;
0356 #interrupt-cells = <1>;
0357 interrupt-parent = <&gic>;
0358 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
0359
0360 ports {
0361 #address-cells = <1>;
0362 #size-cells = <0>;
0363
0364 port@0 {
0365 status = "off";
0366 reg = <0>;
0367 label = "lan0";
0368 };
0369
0370 port@1 {
0371 status = "off";
0372 reg = <1>;
0373 label = "lan1";
0374 };
0375
0376 port@2 {
0377 status = "off";
0378 reg = <2>;
0379 label = "lan2";
0380 };
0381
0382 port@3 {
0383 status = "off";
0384 reg = <3>;
0385 label = "lan3";
0386 };
0387
0388 port@4 {
0389 status = "off";
0390 reg = <4>;
0391 label = "lan4";
0392 };
0393
0394 port@6 {
0395 reg = <6>;
0396 label = "cpu";
0397 ethernet = <&gmac0>;
0398 phy-mode = "trgmii";
0399
0400 fixed-link {
0401 speed = <1000>;
0402 full-duplex;
0403 pause;
0404 };
0405 };
0406 };
0407 };
0408 };
0409 };
0410
0411 pcie: pcie@1e140000 {
0412 compatible = "mediatek,mt7621-pci";
0413 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
0414 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
0415 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
0416 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
0417 #address-cells = <3>;
0418 #size-cells = <2>;
0419
0420 pinctrl-names = "default";
0421 pinctrl-0 = <&pcie_pins>;
0422
0423 device_type = "pci";
0424
0425 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
0426 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
0427
0428 #interrupt-cells = <1>;
0429 interrupt-map-mask = <0xF800 0 0 0>;
0430 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
0431 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
0432 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
0433
0434 status = "disabled";
0435
0436 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
0437
0438 pcie@0,0 {
0439 reg = <0x0000 0 0 0 0>;
0440 #address-cells = <3>;
0441 #size-cells = <2>;
0442 device_type = "pci";
0443 #interrupt-cells = <1>;
0444 interrupt-map-mask = <0 0 0 0>;
0445 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
0446 resets = <&sysc MT7621_RST_PCIE0>;
0447 clocks = <&sysc MT7621_CLK_PCIE0>;
0448 phys = <&pcie0_phy 1>;
0449 phy-names = "pcie-phy0";
0450 ranges;
0451 };
0452
0453 pcie@1,0 {
0454 reg = <0x0800 0 0 0 0>;
0455 #address-cells = <3>;
0456 #size-cells = <2>;
0457 device_type = "pci";
0458 #interrupt-cells = <1>;
0459 interrupt-map-mask = <0 0 0 0>;
0460 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
0461 resets = <&sysc MT7621_RST_PCIE1>;
0462 clocks = <&sysc MT7621_CLK_PCIE1>;
0463 phys = <&pcie0_phy 1>;
0464 phy-names = "pcie-phy1";
0465 ranges;
0466 };
0467
0468 pcie@2,0 {
0469 reg = <0x1000 0 0 0 0>;
0470 #address-cells = <3>;
0471 #size-cells = <2>;
0472 device_type = "pci";
0473 #interrupt-cells = <1>;
0474 interrupt-map-mask = <0 0 0 0>;
0475 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
0476 resets = <&sysc MT7621_RST_PCIE2>;
0477 clocks = <&sysc MT7621_CLK_PCIE2>;
0478 phys = <&pcie2_phy 0>;
0479 phy-names = "pcie-phy2";
0480 ranges;
0481 };
0482 };
0483
0484 pcie0_phy: pcie-phy@1e149000 {
0485 compatible = "mediatek,mt7621-pci-phy";
0486 reg = <0x1e149000 0x0700>;
0487 clocks = <&sysc MT7621_CLK_XTAL>;
0488 #phy-cells = <1>;
0489 };
0490
0491 pcie2_phy: pcie-phy@1e14a000 {
0492 compatible = "mediatek,mt7621-pci-phy";
0493 reg = <0x1e14a000 0x0700>;
0494 clocks = <&sysc MT7621_CLK_XTAL>;
0495 #phy-cells = <1>;
0496 };
0497 };
