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0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/ath79-clk.h>
0003
0004 / {
0005 compatible = "qca,ar9331";
0006
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009
0010 cpus {
0011 #address-cells = <1>;
0012 #size-cells = <0>;
0013
0014 cpu@0 {
0015 device_type = "cpu";
0016 compatible = "mips,mips24Kc";
0017 clocks = <&pll ATH79_CLK_CPU>;
0018 reg = <0>;
0019 };
0020 };
0021
0022 cpuintc: interrupt-controller {
0023 compatible = "qca,ar7100-cpu-intc";
0024
0025 interrupt-controller;
0026 #interrupt-cells = <1>;
0027
0028 qca,ddr-wb-channel-interrupts = <2>, <3>;
0029 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
0030 };
0031
0032 ref: ref {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 };
0036
0037 ahb {
0038 compatible = "simple-bus";
0039 ranges;
0040
0041 #address-cells = <1>;
0042 #size-cells = <1>;
0043
0044 interrupt-parent = <&cpuintc>;
0045
0046 apb {
0047 compatible = "simple-bus";
0048 ranges;
0049
0050 #address-cells = <1>;
0051 #size-cells = <1>;
0052
0053 interrupt-parent = <&miscintc>;
0054
0055 ddr_ctrl: memory-controller@18000000 {
0056 compatible = "qca,ar7240-ddr-controller";
0057 reg = <0x18000000 0x100>;
0058
0059 #qca,ddr-wb-channel-cells = <1>;
0060 };
0061
0062 uart: serial@18020000 {
0063 compatible = "qca,ar9330-uart";
0064 reg = <0x18020000 0x14>;
0065
0066 interrupts = <3>;
0067
0068 clocks = <&ref>;
0069 clock-names = "uart";
0070
0071 status = "disabled";
0072 };
0073
0074 gpio: gpio@18040000 {
0075 compatible = "qca,ar7100-gpio";
0076 reg = <0x18040000 0x34>;
0077 interrupts = <2>;
0078
0079 ngpios = <30>;
0080
0081 gpio-controller;
0082 #gpio-cells = <2>;
0083
0084 interrupt-controller;
0085 #interrupt-cells = <2>;
0086
0087 status = "disabled";
0088 };
0089
0090 pll: pll-controller@18050000 {
0091 compatible = "qca,ar9330-pll";
0092 reg = <0x18050000 0x100>;
0093
0094 clocks = <&ref>;
0095 clock-names = "ref";
0096
0097 #clock-cells = <1>;
0098 };
0099
0100 miscintc: interrupt-controller@18060010 {
0101 compatible = "qca,ar7240-misc-intc";
0102 reg = <0x18060010 0x8>;
0103
0104 interrupt-parent = <&cpuintc>;
0105 interrupts = <6>;
0106
0107 interrupt-controller;
0108 #interrupt-cells = <1>;
0109 };
0110
0111 rst: reset-controller@1806001c {
0112 compatible = "qca,ar7100-reset";
0113 reg = <0x1806001c 0x4>;
0114
0115 #reset-cells = <1>;
0116 };
0117 };
0118
0119 eth0: ethernet@19000000 {
0120 compatible = "qca,ar9330-eth";
0121 reg = <0x19000000 0x200>;
0122 interrupts = <4>;
0123
0124 resets = <&rst 9>, <&rst 22>;
0125 reset-names = "mac", "mdio";
0126 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
0127 clock-names = "eth", "mdio";
0128
0129 phy-mode = "mii";
0130 phy-handle = <&phy_port4>;
0131
0132 status = "disabled";
0133 };
0134
0135 eth1: ethernet@1a000000 {
0136 compatible = "qca,ar9330-eth";
0137 reg = <0x1a000000 0x200>;
0138 interrupts = <5>;
0139 resets = <&rst 13>, <&rst 23>;
0140 reset-names = "mac", "mdio";
0141 clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
0142 clock-names = "eth", "mdio";
0143
0144 phy-mode = "gmii";
0145
0146 status = "disabled";
0147
0148 fixed-link {
0149 speed = <1000>;
0150 full-duplex;
0151 pause;
0152 };
0153
0154 mdio {
0155 #address-cells = <1>;
0156 #size-cells = <0>;
0157
0158 switch10: switch@10 {
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161
0162 compatible = "qca,ar9331-switch";
0163 reg = <0x10>;
0164 resets = <&rst 8>;
0165 reset-names = "switch";
0166
0167 interrupt-parent = <&miscintc>;
0168 interrupts = <12>;
0169
0170 interrupt-controller;
0171 #interrupt-cells = <1>;
0172
0173 ports {
0174 #address-cells = <1>;
0175 #size-cells = <0>;
0176
0177 switch_port0: port@0 {
0178 reg = <0x0>;
0179 label = "cpu";
0180 ethernet = <ð1>;
0181
0182 phy-mode = "gmii";
0183
0184 fixed-link {
0185 speed = <1000>;
0186 full-duplex;
0187 pause;
0188 };
0189 };
0190
0191 switch_port1: port@1 {
0192 reg = <0x1>;
0193 phy-handle = <&phy_port0>;
0194 phy-mode = "internal";
0195
0196 status = "disabled";
0197 };
0198
0199 switch_port2: port@2 {
0200 reg = <0x2>;
0201 phy-handle = <&phy_port1>;
0202 phy-mode = "internal";
0203
0204 status = "disabled";
0205 };
0206
0207 switch_port3: port@3 {
0208 reg = <0x3>;
0209 phy-handle = <&phy_port2>;
0210 phy-mode = "internal";
0211
0212 status = "disabled";
0213 };
0214
0215 switch_port4: port@4 {
0216 reg = <0x4>;
0217 phy-handle = <&phy_port3>;
0218 phy-mode = "internal";
0219
0220 status = "disabled";
0221 };
0222 };
0223
0224 mdio {
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227
0228 interrupt-parent = <&switch10>;
0229
0230 phy_port0: phy@0 {
0231 reg = <0x0>;
0232 interrupts = <0>;
0233 status = "disabled";
0234 };
0235
0236 phy_port1: phy@1 {
0237 reg = <0x1>;
0238 interrupts = <0>;
0239 status = "disabled";
0240 };
0241
0242 phy_port2: phy@2 {
0243 reg = <0x2>;
0244 interrupts = <0>;
0245 status = "disabled";
0246 };
0247
0248 phy_port3: phy@3 {
0249 reg = <0x3>;
0250 interrupts = <0>;
0251 status = "disabled";
0252 };
0253
0254 phy_port4: phy@4 {
0255 reg = <0x4>;
0256 interrupts = <0>;
0257 status = "disabled";
0258 };
0259 };
0260 };
0261 };
0262 };
0263
0264 usb: usb@1b000100 {
0265 compatible = "chipidea,usb2";
0266 reg = <0x1b000000 0x200>;
0267
0268 interrupts = <3>;
0269 resets = <&rst 5>;
0270
0271 phy-names = "usb-phy";
0272 phys = <&usb_phy>;
0273
0274 status = "disabled";
0275 };
0276
0277 spi: spi@1f000000 {
0278 compatible = "qca,ar7100-spi";
0279 reg = <0x1f000000 0x10>;
0280
0281 clocks = <&pll ATH79_CLK_AHB>;
0282 clock-names = "ahb";
0283
0284 #address-cells = <1>;
0285 #size-cells = <0>;
0286
0287 status = "disabled";
0288 };
0289 };
0290
0291 usb_phy: usb-phy {
0292 compatible = "qca,ar7100-usb-phy";
0293
0294 reset-names = "phy", "suspend-override";
0295 resets = <&rst 4>, <&rst 3>;
0296
0297 #phy-cells = <0>;
0298
0299 status = "disabled";
0300 };
0301 };
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