0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/ath79-clk.h>
0003
0004 / {
0005 compatible = "qca,ar9132";
0006
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009
0010 cpus {
0011 #address-cells = <1>;
0012 #size-cells = <0>;
0013
0014 cpu@0 {
0015 device_type = "cpu";
0016 compatible = "mips,mips24Kc";
0017 clocks = <&pll ATH79_CLK_CPU>;
0018 reg = <0>;
0019 };
0020 };
0021
0022 cpuintc: interrupt-controller {
0023 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
0024
0025 interrupt-controller;
0026 #interrupt-cells = <1>;
0027
0028 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
0029 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
0030 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
0031 };
0032
0033 ahb {
0034 compatible = "simple-bus";
0035 ranges;
0036
0037 #address-cells = <1>;
0038 #size-cells = <1>;
0039
0040 interrupt-parent = <&cpuintc>;
0041
0042 apb {
0043 compatible = "simple-bus";
0044 ranges;
0045
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048
0049 interrupt-parent = <&miscintc>;
0050
0051 ddr_ctrl: memory-controller@18000000 {
0052 compatible = "qca,ar9132-ddr-controller",
0053 "qca,ar7240-ddr-controller";
0054 reg = <0x18000000 0x100>;
0055
0056 #qca,ddr-wb-channel-cells = <1>;
0057 };
0058
0059 uart: uart@18020000 {
0060 compatible = "ns8250";
0061 reg = <0x18020000 0x20>;
0062 interrupts = <3>;
0063
0064 clocks = <&pll ATH79_CLK_AHB>;
0065 clock-names = "uart";
0066
0067 reg-io-width = <4>;
0068 reg-shift = <2>;
0069 no-loopback-test;
0070
0071 status = "disabled";
0072 };
0073
0074 gpio: gpio@18040000 {
0075 compatible = "qca,ar9132-gpio",
0076 "qca,ar7100-gpio";
0077 reg = <0x18040000 0x30>;
0078 interrupts = <2>;
0079
0080 ngpios = <22>;
0081
0082 gpio-controller;
0083 #gpio-cells = <2>;
0084
0085 interrupt-controller;
0086 #interrupt-cells = <2>;
0087 };
0088
0089 pll: pll-controller@18050000 {
0090 compatible = "qca,ar9132-pll",
0091 "qca,ar9130-pll";
0092 reg = <0x18050000 0x20>;
0093
0094 clock-names = "ref";
0095 /* The board must provides the ref clock */
0096
0097 #clock-cells = <1>;
0098 clock-output-names = "cpu", "ddr", "ahb";
0099 };
0100
0101 wdt: wdt@18060008 {
0102 compatible = "qca,ar7130-wdt";
0103 reg = <0x18060008 0x8>;
0104
0105 interrupts = <4>;
0106
0107 clocks = <&pll ATH79_CLK_AHB>;
0108 clock-names = "wdt";
0109 };
0110
0111 miscintc: interrupt-controller@18060010 {
0112 compatible = "qca,ar9132-misc-intc",
0113 "qca,ar7100-misc-intc";
0114 reg = <0x18060010 0x8>;
0115
0116 interrupt-parent = <&cpuintc>;
0117 interrupts = <6>;
0118
0119 interrupt-controller;
0120 #interrupt-cells = <1>;
0121 };
0122
0123 rst: reset-controller@1806001c {
0124 compatible = "qca,ar9132-reset",
0125 "qca,ar7100-reset";
0126 reg = <0x1806001c 0x4>;
0127
0128 #reset-cells = <1>;
0129 };
0130 };
0131
0132 usb: usb@1b000100 {
0133 compatible = "qca,ar7100-ehci", "generic-ehci";
0134 reg = <0x1b000100 0x100>;
0135
0136 interrupts = <3>;
0137 resets = <&rst 5>;
0138
0139 has-transaction-translator;
0140
0141 phy-names = "usb";
0142 phys = <&usb_phy>;
0143
0144 status = "disabled";
0145 };
0146
0147 spi: spi@1f000000 {
0148 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
0149 reg = <0x1f000000 0x10>;
0150
0151 clocks = <&pll ATH79_CLK_AHB>;
0152 clock-names = "ahb";
0153
0154 status = "disabled";
0155
0156 #address-cells = <1>;
0157 #size-cells = <0>;
0158 };
0159 };
0160
0161 usb_phy: usb-phy {
0162 compatible = "qca,ar7100-usb-phy";
0163
0164 reset-names = "phy", "suspend-override";
0165 resets = <&rst 4>, <&rst 3>;
0166
0167 #phy-cells = <0>;
0168
0169 status = "disabled";
0170 };
0171 };
