0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
0004 */
0005 #include <dt-bindings/clock/microchip,pic32-clock.h>
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 interrupt-parent = <&evic>;
0012
0013 aliases {
0014 gpio0 = &gpio0;
0015 gpio1 = &gpio1;
0016 gpio2 = &gpio2;
0017 gpio3 = &gpio3;
0018 gpio4 = &gpio4;
0019 gpio5 = &gpio5;
0020 gpio6 = &gpio6;
0021 gpio7 = &gpio7;
0022 gpio8 = &gpio8;
0023 gpio9 = &gpio9;
0024 serial0 = &uart1;
0025 serial1 = &uart2;
0026 serial2 = &uart3;
0027 serial3 = &uart4;
0028 serial4 = &uart5;
0029 serial5 = &uart6;
0030 };
0031
0032 cpus {
0033 #address-cells = <1>;
0034 #size-cells = <0>;
0035
0036 cpu@0 {
0037 compatible = "mti,mips14KEc";
0038 device_type = "cpu";
0039 };
0040 };
0041
0042 soc {
0043 compatible = "microchip,pic32mzda-infra";
0044 interrupts = <0 IRQ_TYPE_EDGE_RISING>;
0045 };
0046
0047 /* external clock input on TxCLKI pin */
0048 txcki: txcki_clk {
0049 #clock-cells = <0>;
0050 compatible = "fixed-clock";
0051 clock-frequency = <4000000>;
0052 status = "disabled";
0053 };
0054
0055 /* external input on REFCLKIx pin */
0056 refix: refix_clk {
0057 #clock-cells = <0>;
0058 compatible = "fixed-clock";
0059 clock-frequency = <24000000>;
0060 status = "disabled";
0061 };
0062
0063 rootclk: clock-controller@1f801200 {
0064 compatible = "microchip,pic32mzda-clk";
0065 reg = <0x1f801200 0x200>;
0066 #clock-cells = <1>;
0067 microchip,pic32mzda-sosc;
0068 };
0069
0070 evic: interrupt-controller@1f810000 {
0071 compatible = "microchip,pic32mzda-evic";
0072 interrupt-controller;
0073 #interrupt-cells = <2>;
0074 reg = <0x1f810000 0x1000>;
0075 microchip,external-irqs = <3 8 13 18 23>;
0076 };
0077
0078 pic32_pinctrl: pinctrl@1f801400{
0079 #address-cells = <1>;
0080 #size-cells = <1>;
0081 compatible = "microchip,pic32mzda-pinctrl";
0082 reg = <0x1f801400 0x400>;
0083 clocks = <&rootclk PB1CLK>;
0084 };
0085
0086 /* PORTA */
0087 gpio0: gpio0@1f860000 {
0088 compatible = "microchip,pic32mzda-gpio";
0089 reg = <0x1f860000 0x100>;
0090 interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
0091 #gpio-cells = <2>;
0092 gpio-controller;
0093 interrupt-controller;
0094 #interrupt-cells = <2>;
0095 clocks = <&rootclk PB4CLK>;
0096 microchip,gpio-bank = <0>;
0097 gpio-ranges = <&pic32_pinctrl 0 0 16>;
0098 };
0099
0100 /* PORTB */
0101 gpio1: gpio1@1f860100 {
0102 compatible = "microchip,pic32mzda-gpio";
0103 reg = <0x1f860100 0x100>;
0104 interrupts = <119 IRQ_TYPE_LEVEL_HIGH>;
0105 #gpio-cells = <2>;
0106 gpio-controller;
0107 interrupt-controller;
0108 #interrupt-cells = <2>;
0109 clocks = <&rootclk PB4CLK>;
0110 microchip,gpio-bank = <1>;
0111 gpio-ranges = <&pic32_pinctrl 0 16 16>;
0112 };
0113
0114 /* PORTC */
0115 gpio2: gpio2@1f860200 {
0116 compatible = "microchip,pic32mzda-gpio";
0117 reg = <0x1f860200 0x100>;
0118 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
0119 #gpio-cells = <2>;
0120 gpio-controller;
0121 interrupt-controller;
0122 #interrupt-cells = <2>;
0123 clocks = <&rootclk PB4CLK>;
0124 microchip,gpio-bank = <2>;
0125 gpio-ranges = <&pic32_pinctrl 0 32 16>;
0126 };
0127
0128 /* PORTD */
0129 gpio3: gpio3@1f860300 {
0130 compatible = "microchip,pic32mzda-gpio";
0131 reg = <0x1f860300 0x100>;
0132 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
0133 #gpio-cells = <2>;
0134 gpio-controller;
0135 interrupt-controller;
0136 #interrupt-cells = <2>;
0137 clocks = <&rootclk PB4CLK>;
0138 microchip,gpio-bank = <3>;
0139 gpio-ranges = <&pic32_pinctrl 0 48 16>;
0140 };
0141
0142 /* PORTE */
0143 gpio4: gpio4@1f860400 {
0144 compatible = "microchip,pic32mzda-gpio";
0145 reg = <0x1f860400 0x100>;
0146 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
0147 #gpio-cells = <2>;
0148 gpio-controller;
0149 interrupt-controller;
0150 #interrupt-cells = <2>;
0151 clocks = <&rootclk PB4CLK>;
0152 microchip,gpio-bank = <4>;
0153 gpio-ranges = <&pic32_pinctrl 0 64 16>;
0154 };
0155
0156 /* PORTF */
0157 gpio5: gpio5@1f860500 {
0158 compatible = "microchip,pic32mzda-gpio";
0159 reg = <0x1f860500 0x100>;
0160 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
0161 #gpio-cells = <2>;
0162 gpio-controller;
0163 interrupt-controller;
0164 #interrupt-cells = <2>;
0165 clocks = <&rootclk PB4CLK>;
0166 microchip,gpio-bank = <5>;
0167 gpio-ranges = <&pic32_pinctrl 0 80 16>;
0168 };
0169
0170 /* PORTG */
0171 gpio6: gpio6@1f860600 {
0172 compatible = "microchip,pic32mzda-gpio";
0173 reg = <0x1f860600 0x100>;
0174 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
0175 #gpio-cells = <2>;
0176 gpio-controller;
0177 interrupt-controller;
0178 #interrupt-cells = <2>;
0179 clocks = <&rootclk PB4CLK>;
0180 microchip,gpio-bank = <6>;
0181 gpio-ranges = <&pic32_pinctrl 0 96 16>;
0182 };
0183
0184 /* PORTH */
0185 gpio7: gpio7@1f860700 {
0186 compatible = "microchip,pic32mzda-gpio";
0187 reg = <0x1f860700 0x100>;
0188 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
0189 #gpio-cells = <2>;
0190 gpio-controller;
0191 interrupt-controller;
0192 #interrupt-cells = <2>;
0193 clocks = <&rootclk PB4CLK>;
0194 microchip,gpio-bank = <7>;
0195 gpio-ranges = <&pic32_pinctrl 0 112 16>;
0196 };
0197
0198 /* PORTI does not exist */
0199
0200 /* PORTJ */
0201 gpio8: gpio8@1f860800 {
0202 compatible = "microchip,pic32mzda-gpio";
0203 reg = <0x1f860800 0x100>;
0204 interrupts = <126 IRQ_TYPE_LEVEL_HIGH>;
0205 #gpio-cells = <2>;
0206 gpio-controller;
0207 interrupt-controller;
0208 #interrupt-cells = <2>;
0209 clocks = <&rootclk PB4CLK>;
0210 microchip,gpio-bank = <8>;
0211 gpio-ranges = <&pic32_pinctrl 0 128 16>;
0212 };
0213
0214 /* PORTK */
0215 gpio9: gpio9@1f860900 {
0216 compatible = "microchip,pic32mzda-gpio";
0217 reg = <0x1f860900 0x100>;
0218 interrupts = <127 IRQ_TYPE_LEVEL_HIGH>;
0219 #gpio-cells = <2>;
0220 gpio-controller;
0221 interrupt-controller;
0222 #interrupt-cells = <2>;
0223 clocks = <&rootclk PB4CLK>;
0224 microchip,gpio-bank = <9>;
0225 gpio-ranges = <&pic32_pinctrl 0 144 16>;
0226 };
0227
0228 sdhci: sdhci@1f8ec000 {
0229 compatible = "microchip,pic32mzda-sdhci";
0230 reg = <0x1f8ec000 0x100>;
0231 interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
0232 clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
0233 clock-names = "base_clk", "sys_clk";
0234 bus-width = <4>;
0235 cap-sd-highspeed;
0236 status = "disabled";
0237 };
0238
0239 uart1: serial@1f822000 {
0240 compatible = "microchip,pic32mzda-uart";
0241 reg = <0x1f822000 0x50>;
0242 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
0243 <113 IRQ_TYPE_LEVEL_HIGH>,
0244 <114 IRQ_TYPE_LEVEL_HIGH>;
0245 clocks = <&rootclk PB2CLK>;
0246 status = "disabled";
0247 };
0248
0249 uart2: serial@1f822200 {
0250 compatible = "microchip,pic32mzda-uart";
0251 reg = <0x1f822200 0x50>;
0252 interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
0253 <146 IRQ_TYPE_LEVEL_HIGH>,
0254 <147 IRQ_TYPE_LEVEL_HIGH>;
0255 clocks = <&rootclk PB2CLK>;
0256 status = "disabled";
0257 };
0258
0259 uart3: serial@1f822400 {
0260 compatible = "microchip,pic32mzda-uart";
0261 reg = <0x1f822400 0x50>;
0262 interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
0263 <158 IRQ_TYPE_LEVEL_HIGH>,
0264 <159 IRQ_TYPE_LEVEL_HIGH>;
0265 clocks = <&rootclk PB2CLK>;
0266 status = "disabled";
0267 };
0268
0269 uart4: serial@1f822600 {
0270 compatible = "microchip,pic32mzda-uart";
0271 reg = <0x1f822600 0x50>;
0272 interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
0273 <171 IRQ_TYPE_LEVEL_HIGH>,
0274 <172 IRQ_TYPE_LEVEL_HIGH>;
0275 clocks = <&rootclk PB2CLK>;
0276 status = "disabled";
0277 };
0278
0279 uart5: serial@1f822800 {
0280 compatible = "microchip,pic32mzda-uart";
0281 reg = <0x1f822800 0x50>;
0282 interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
0283 <180 IRQ_TYPE_LEVEL_HIGH>,
0284 <181 IRQ_TYPE_LEVEL_HIGH>;
0285 clocks = <&rootclk PB2CLK>;
0286 status = "disabled";
0287 };
0288
0289 uart6: serial@1f822A00 {
0290 compatible = "microchip,pic32mzda-uart";
0291 reg = <0x1f822A00 0x50>;
0292 interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
0293 <189 IRQ_TYPE_LEVEL_HIGH>,
0294 <190 IRQ_TYPE_LEVEL_HIGH>;
0295 clocks = <&rootclk PB2CLK>;
0296 status = "disabled";
0297 };
0298 };
