0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/interrupt-controller/irq.h>
0005 #include <dt-bindings/interrupt-controller/mips-gic.h>
0006
0007 /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
0008 /memreserve/ 0x00001000 0x000ef000; /* YAMON */
0009 /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 compatible = "mti,malta";
0015
0016 cpu_intc: interrupt-controller {
0017 compatible = "mti,cpu-interrupt-controller";
0018
0019 interrupt-controller;
0020 #interrupt-cells = <1>;
0021 };
0022
0023 gic: interrupt-controller@1bdc0000 {
0024 compatible = "mti,gic";
0025 reg = <0x1bdc0000 0x20000>;
0026
0027 interrupt-controller;
0028 #interrupt-cells = <3>;
0029
0030 /*
0031 * Declare the interrupt-parent even though the mti,gic
0032 * binding doesn't require it, such that the kernel can
0033 * figure out that cpu_intc is the root interrupt
0034 * controller & should be probed first.
0035 */
0036 interrupt-parent = <&cpu_intc>;
0037
0038 timer {
0039 compatible = "mti,gic-timer";
0040 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
0041 };
0042 };
0043
0044 i8259: interrupt-controller@20 {
0045 compatible = "intel,i8259";
0046
0047 interrupt-controller;
0048 #interrupt-cells = <1>;
0049
0050 interrupt-parent = <&gic>;
0051 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
0052 };
0053
0054 flash@1e000000 {
0055 compatible = "intel,dt28f160", "cfi-flash";
0056 reg = <0x1e000000 0x400000>;
0057 bank-width = <4>;
0058 #address-cells = <1>;
0059 #size-cells = <1>;
0060
0061 partitions {
0062 compatible = "fixed-partitions";
0063 #address-cells = <1>;
0064 #size-cells = <1>;
0065
0066 yamon@0 {
0067 label = "YAMON";
0068 reg = <0x0 0x100000>;
0069 read-only;
0070 };
0071
0072 user-fs@100000 {
0073 label = "User FS";
0074 reg = <0x100000 0x2e0000>;
0075 };
0076
0077 board-config@3e0000 {
0078 label = "Board Config";
0079 reg = <0x3e0000 0x20000>;
0080 read-only;
0081 };
0082 };
0083 };
0084
0085 fpga_regs: system-controller@1f000000 {
0086 compatible = "mti,malta-fpga", "syscon", "simple-mfd";
0087 reg = <0x1f000000 0x1000>;
0088 native-endian;
0089
0090 lcd@410 {
0091 compatible = "mti,malta-lcd";
0092 offset = <0x410>;
0093 };
0094
0095 reboot {
0096 compatible = "syscon-reboot";
0097 regmap = <&fpga_regs>;
0098 offset = <0x500>;
0099 mask = <0x42>;
0100 };
0101 };
0102
0103 isa {
0104 compatible = "isa";
0105 #address-cells = <2>;
0106 #size-cells = <1>;
0107 ranges = <1 0 0 0x1000>;
0108
0109 rtc@70 {
0110 compatible = "motorola,mc146818";
0111 reg = <1 0x70 0x8>;
0112
0113 interrupt-parent = <&i8259>;
0114 interrupts = <8>;
0115 };
0116 };
0117 };
