0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2018 Microsemi Corporation
0004 */
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 compatible = "mscc,serval";
0010
0011 cpus {
0012 #address-cells = <1>;
0013 #size-cells = <0>;
0014
0015 cpu@0 {
0016 compatible = "mips,mips24KEc";
0017 device_type = "cpu";
0018 clocks = <&cpu_clk>;
0019 reg = <0>;
0020 };
0021 };
0022
0023 aliases {
0024 serial0 = &uart0;
0025 gpio0 = &gpio;
0026 };
0027
0028 cpuintc: interrupt-controller {
0029 #address-cells = <0>;
0030 #interrupt-cells = <1>;
0031 interrupt-controller;
0032 compatible = "mti,cpu-interrupt-controller";
0033 };
0034
0035 cpu_clk: cpu-clock {
0036 compatible = "fixed-clock";
0037 #clock-cells = <0>;
0038 clock-frequency = <416666666>;
0039 };
0040
0041 ahb_clk: ahb-clk {
0042 compatible = "fixed-factor-clock";
0043 #clock-cells = <0>;
0044 clocks = <&cpu_clk>;
0045 clock-div = <2>;
0046 clock-mult = <1>;
0047 };
0048
0049 ahb: ahb {
0050 compatible = "simple-bus";
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053 ranges;
0054
0055 interrupt-parent = <&intc>;
0056
0057 cpu_ctrl: syscon@70000000 {
0058 compatible = "mscc,ocelot-cpu-syscon", "syscon";
0059 reg = <0x70000000 0x2c>;
0060 };
0061
0062 intc: interrupt-controller@70000070 {
0063 compatible = "mscc,serval-icpu-intr";
0064 reg = <0x70000070 0x70>;
0065 #interrupt-cells = <1>;
0066 interrupt-controller;
0067 interrupt-parent = <&cpuintc>;
0068 interrupts = <2>;
0069 };
0070
0071 uart0: serial@70100000 {
0072 pinctrl-0 = <&uart_pins>;
0073 pinctrl-names = "default";
0074 compatible = "ns16550a";
0075 reg = <0x70100000 0x20>;
0076 interrupts = <6>;
0077 clocks = <&ahb_clk>;
0078 reg-io-width = <4>;
0079 reg-shift = <2>;
0080
0081 status = "disabled";
0082 };
0083
0084 uart2: serial@70100800 {
0085 pinctrl-0 = <&uart2_pins>;
0086 pinctrl-names = "default";
0087 compatible = "ns16550a";
0088 reg = <0x70100800 0x20>;
0089 interrupts = <7>;
0090 clocks = <&ahb_clk>;
0091 reg-io-width = <4>;
0092 reg-shift = <2>;
0093
0094 status = "disabled";
0095 };
0096
0097 gpio: pinctrl@71070034 {
0098 compatible = "mscc,serval-pinctrl";
0099 reg = <0x71070034 0x28>;
0100 gpio-controller;
0101 #gpio-cells = <2>;
0102 gpio-ranges = <&gpio 0 0 22>;
0103
0104 sgpio_pins: sgpio-pins {
0105 pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
0106 function = "sg0";
0107 };
0108
0109 i2c_pins: i2c-pins {
0110 pins = "GPIO_6", "GPIO_7";
0111 function = "twi";
0112 };
0113
0114 uart_pins: uart-pins {
0115 pins = "GPIO_26", "GPIO_27";
0116 function = "uart";
0117 };
0118
0119 uart2_pins: uart2-pins {
0120 pins = "GPIO_13", "GPIO_14";
0121 function = "uart2";
0122 };
0123
0124 cs1_pins: cs1-pins {
0125 pins = "GPIO_8";
0126 function = "si";
0127 };
0128
0129 irqext0_pins: irqext0-pins {
0130 pins = "GPIO_28";
0131 function = "irq0";
0132 };
0133
0134 irqext1_pins: irqext1-pins {
0135 pins = "GPIO_29";
0136 function = "irq1";
0137 };
0138 };
0139
0140 i2c0: i2c@70100400 {
0141 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
0142 status = "disabled";
0143 pinctrl-0 = <&i2c_pins>;
0144 pinctrl-names = "default";
0145 reg = <0x70100400 0x100>, <0x70000190 0x8>;
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148 interrupts = <8>;
0149 clock-frequency = <100000>;
0150 clocks = <&ahb_clk>;
0151 };
0152 };
0153 };
