dts/mscc/ocelot_pcb120.dts

0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /* Copyright (c) 2017 Microsemi Corporation */
0003
0004 /dts-v1/;
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008 #include <dt-bindings/phy/phy-ocelot-serdes.h>
0009 #include "ocelot.dtsi"
0010
0011 / {
0012         compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
0013
0014         chosen {
0015                 stdout-path = "serial0:115200n8";
0016         };
0017
0018         memory@0 {
0019                 device_type = "memory";
0020                 reg = <0x0 0x0e000000>;
0021         };
0022 };
0023
0024 &gpio {
0025         phy_int_pins: phy-int-pins {
0026                 pins = "GPIO_4";
0027                 function = "gpio";
0028         };
0029
0030         phy_load_save_pins: phy-load-save-pins {
0031                 pins = "GPIO_10";
0032                 function = "ptp2";
0033         };
0034 };
0035
0036 &mdio0 {
0037         status = "okay";
0038 };
0039
0040 &mdio1 {
0041         status = "okay";
0042         pinctrl-names = "default";
0043         pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
0044
0045         phy7: ethernet-phy@0 {
0046                 reg = <0>;
0047                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0048                 interrupt-parent = <&gpio>;
0049                 load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
0050         };
0051         phy6: ethernet-phy@1 {
0052                 reg = <1>;
0053                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0054                 interrupt-parent = <&gpio>;
0055                 load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
0056         };
0057         phy5: ethernet-phy@2 {
0058                 reg = <2>;
0059                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0060                 interrupt-parent = <&gpio>;
0061                 load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
0062         };
0063         phy4: ethernet-phy@3 {
0064                 reg = <3>;
0065                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0066                 interrupt-parent = <&gpio>;
0067                 load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
0068         };
0069 };
0070
0071 &port0 {
0072         status = "okay";
0073         phy-handle = <&phy0>;
0074         phy-mode = "internal";
0075 };
0076
0077 &port1 {
0078         status = "okay";
0079         phy-handle = <&phy1>;
0080         phy-mode = "internal";
0081 };
0082
0083 &port2 {
0084         status = "okay";
0085         phy-handle = <&phy2>;
0086         phy-mode = "internal";
0087 };
0088
0089 &port3 {
0090         status = "okay";
0091         phy-handle = <&phy3>;
0092         phy-mode = "internal";
0093 };
0094
0095 &port4 {
0096         status = "okay";
0097         phy-handle = <&phy7>;
0098         phy-mode = "sgmii";
0099         phys = <&serdes 4 SERDES1G(2)>;
0100 };
0101
0102 &port5 {
0103         status = "okay";
0104         phy-handle = <&phy4>;
0105         phy-mode = "sgmii";
0106         phys = <&serdes 5 SERDES1G(5)>;
0107 };
0108
0109 &port6 {
0110         status = "okay";
0111         phy-handle = <&phy6>;
0112         phy-mode = "sgmii";
0113         phys = <&serdes 6 SERDES1G(3)>;
0114 };
0115
0116 &port9 {
0117         status = "okay";
0118         phy-handle = <&phy5>;
0119         phy-mode = "sgmii";
0120         phys = <&serdes 9 SERDES1G(4)>;
0121 };
0122
0123 &uart0 {
0124         status = "okay";
0125 };
0126
0127 &uart2 {
0128         status = "okay";
0129 };