OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /* Copyright (c) 2017 Microsemi Corporation */
0003
0004 / {
0005 #address-cells = <1>;
0006 #size-cells = <1>;
0007 compatible = "mscc,ocelot";
0008
0009 cpus {
0010 #address-cells = <1>;
0011 #size-cells = <0>;
0012
0013 cpu@0 {
0014 compatible = "mips,mips24KEc";
0015 device_type = "cpu";
0016 clocks = <&cpu_clk>;
0017 reg = <0>;
0018 };
0019 };
0020
0021 aliases {
0022 serial0 = &uart0;
0023 };
0024
0025 cpuintc: interrupt-controller {
0026 #address-cells = <0>;
0027 #interrupt-cells = <1>;
0028 interrupt-controller;
0029 compatible = "mti,cpu-interrupt-controller";
0030 };
0031
0032 cpu_clk: cpu-clock {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 clock-frequency = <500000000>;
0036 };
0037
0038 ahb_clk: ahb-clk {
0039 compatible = "fixed-factor-clock";
0040 #clock-cells = <0>;
0041 clocks = <&cpu_clk>;
0042 clock-div = <2>;
0043 clock-mult = <1>;
0044 };
0045
0046 ahb@70000000 {
0047 compatible = "simple-bus";
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050 ranges = <0 0x70000000 0x2000000>;
0051
0052 interrupt-parent = <&intc>;
0053
0054 cpu_ctrl: syscon@0 {
0055 compatible = "mscc,ocelot-cpu-syscon", "syscon";
0056 reg = <0x0 0x2c>;
0057 };
0058
0059 intc: interrupt-controller@70 {
0060 compatible = "mscc,ocelot-icpu-intr";
0061 reg = <0x70 0x70>;
0062 #interrupt-cells = <1>;
0063 interrupt-controller;
0064 interrupt-parent = <&cpuintc>;
0065 interrupts = <2>;
0066 };
0067
0068 uart0: serial@100000 {
0069 pinctrl-0 = <&uart_pins>;
0070 pinctrl-names = "default";
0071 compatible = "ns16550a";
0072 reg = <0x100000 0x20>;
0073 interrupts = <6>;
0074 clocks = <&ahb_clk>;
0075 reg-io-width = <4>;
0076 reg-shift = <2>;
0077
0078 status = "disabled";
0079 };
0080
0081 i2c: i2c@100400 {
0082 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
0083 pinctrl-0 = <&i2c_pins>;
0084 pinctrl-names = "default";
0085 reg = <0x100400 0x100>, <0x198 0x8>;
0086 #address-cells = <1>;
0087 #size-cells = <0>;
0088 interrupts = <8>;
0089 clocks = <&ahb_clk>;
0090
0091 status = "disabled";
0092 };
0093
0094 uart2: serial@100800 {
0095 pinctrl-0 = <&uart2_pins>;
0096 pinctrl-names = "default";
0097 compatible = "ns16550a";
0098 reg = <0x100800 0x20>;
0099 interrupts = <7>;
0100 clocks = <&ahb_clk>;
0101 reg-io-width = <4>;
0102 reg-shift = <2>;
0103
0104 status = "disabled";
0105 };
0106
0107 spi: spi@101000 {
0108 compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111 reg = <0x101000 0x100>, <0x3c 0x18>;
0112 interrupts = <9>;
0113 clocks = <&ahb_clk>;
0114
0115 status = "disabled";
0116 };
0117
0118 switch@1010000 {
0119 compatible = "mscc,vsc7514-switch";
0120 reg = <0x1010000 0x10000>,
0121 <0x1030000 0x10000>,
0122 <0x1080000 0x100>,
0123 <0x10e0000 0x10000>,
0124 <0x11e0000 0x100>,
0125 <0x11f0000 0x100>,
0126 <0x1200000 0x100>,
0127 <0x1210000 0x100>,
0128 <0x1220000 0x100>,
0129 <0x1230000 0x100>,
0130 <0x1240000 0x100>,
0131 <0x1250000 0x100>,
0132 <0x1260000 0x100>,
0133 <0x1270000 0x100>,
0134 <0x1280000 0x100>,
0135 <0x1800000 0x80000>,
0136 <0x1880000 0x10000>,
0137 <0x1040000 0x10000>,
0138 <0x1050000 0x10000>,
0139 <0x1060000 0x10000>,
0140 <0x1a0 0x1c4>;
0141 reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
0142 "port2", "port3", "port4", "port5", "port6",
0143 "port7", "port8", "port9", "port10", "qsys",
0144 "ana", "s0", "s1", "s2", "fdma";
0145 interrupts = <18 21 22 16>;
0146 interrupt-names = "ptp_rdy", "xtr", "inj", "fdma";
0147
0148 ethernet-ports {
0149 #address-cells = <1>;
0150 #size-cells = <0>;
0151
0152 port0: port@0 {
0153 reg = <0>;
0154 status = "disabled";
0155 };
0156 port1: port@1 {
0157 reg = <1>;
0158 status = "disabled";
0159 };
0160 port2: port@2 {
0161 reg = <2>;
0162 status = "disabled";
0163 };
0164 port3: port@3 {
0165 reg = <3>;
0166 status = "disabled";
0167 };
0168 port4: port@4 {
0169 reg = <4>;
0170 status = "disabled";
0171 };
0172 port5: port@5 {
0173 reg = <5>;
0174 status = "disabled";
0175 };
0176 port6: port@6 {
0177 reg = <6>;
0178 status = "disabled";
0179 };
0180 port7: port@7 {
0181 reg = <7>;
0182 status = "disabled";
0183 };
0184 port8: port@8 {
0185 reg = <8>;
0186 status = "disabled";
0187 };
0188 port9: port@9 {
0189 reg = <9>;
0190 status = "disabled";
0191 };
0192 port10: port@10 {
0193 reg = <10>;
0194 status = "disabled";
0195 };
0196 };
0197 };
0198
0199 reset@1070008 {
0200 compatible = "mscc,ocelot-chip-reset";
0201 reg = <0x1070008 0x4>;
0202 };
0203
0204 gpio: pinctrl@1070034 {
0205 compatible = "mscc,ocelot-pinctrl";
0206 reg = <0x1070034 0x68>;
0207 gpio-controller;
0208 #gpio-cells = <2>;
0209 gpio-ranges = <&gpio 0 0 22>;
0210 interrupt-controller;
0211 interrupts = <13>;
0212 #interrupt-cells = <2>;
0213
0214 i2c_pins: i2c-pins {
0215 pins = "GPIO_16", "GPIO_17";
0216 function = "twi";
0217 };
0218
0219 uart_pins: uart-pins {
0220 pins = "GPIO_6", "GPIO_7";
0221 function = "uart";
0222 };
0223
0224 uart2_pins: uart2-pins {
0225 pins = "GPIO_12", "GPIO_13";
0226 function = "uart2";
0227 };
0228
0229 miim1_pins: miim1-pins {
0230 pins = "GPIO_14", "GPIO_15";
0231 function = "miim";
0232 };
0233
0234 };
0235
0236 mdio0: mdio@107009c {
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239 compatible = "mscc,ocelot-miim";
0240 reg = <0x107009c 0x24>, <0x10700f0 0x8>;
0241 interrupts = <14>;
0242 status = "disabled";
0243
0244 phy0: ethernet-phy@0 {
0245 reg = <0>;
0246 };
0247 phy1: ethernet-phy@1 {
0248 reg = <1>;
0249 };
0250 phy2: ethernet-phy@2 {
0251 reg = <2>;
0252 };
0253 phy3: ethernet-phy@3 {
0254 reg = <3>;
0255 };
0256 };
0257
0258 mdio1: mdio@10700c0 {
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261 compatible = "mscc,ocelot-miim";
0262 reg = <0x10700c0 0x24>;
0263 interrupts = <15>;
0264 pinctrl-names = "default";
0265 pinctrl-0 = <&miim1_pins>;
0266 status = "disabled";
0267 };
0268
0269 hsio: syscon@10d0000 {
0270 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
0271 reg = <0x10d0000 0x10000>;
0272
0273 serdes: serdes {
0274 compatible = "mscc,vsc7514-serdes";
0275 #phy-cells = <2>;
0276 };
0277 };
0278 };
0279 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|