0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2020 Microsemi Corporation
0004 */
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 compatible = "mscc,jr2";
0010
0011 aliases {
0012 serial0 = &uart0;
0013 serial1 = &uart2;
0014 gpio0 = &gpio;
0015 };
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu@0 {
0022 compatible = "mips,mips24KEc";
0023 device_type = "cpu";
0024 clocks = <&cpu_clk>;
0025 reg = <0>;
0026 };
0027 };
0028
0029 cpuintc: interrupt-controller {
0030 #address-cells = <0>;
0031 #interrupt-cells = <1>;
0032 interrupt-controller;
0033 compatible = "mti,cpu-interrupt-controller";
0034 };
0035
0036 cpu_clk: cpu-clock {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <500000000>;
0040 };
0041
0042 ahb_clk: ahb-clk {
0043 compatible = "fixed-factor-clock";
0044 #clock-cells = <0>;
0045 clocks = <&cpu_clk>;
0046 clock-div = <2>;
0047 clock-mult = <1>;
0048 };
0049
0050 ahb: ahb {
0051 compatible = "simple-bus";
0052 #address-cells = <1>;
0053 #size-cells = <1>;
0054 ranges;
0055
0056 interrupt-parent = <&intc>;
0057
0058 cpu_ctrl: syscon@70000000 {
0059 compatible = "mscc,ocelot-cpu-syscon", "syscon";
0060 reg = <0x70000000 0x2c>;
0061 };
0062
0063 intc: interrupt-controller@70000070 {
0064 compatible = "mscc,jaguar2-icpu-intr";
0065 reg = <0x70000070 0x94>;
0066 #interrupt-cells = <1>;
0067 interrupt-controller;
0068 interrupt-parent = <&cpuintc>;
0069 interrupts = <2>;
0070 };
0071
0072 uart0: serial@70100000 {
0073 pinctrl-0 = <&uart_pins>;
0074 pinctrl-names = "default";
0075 compatible = "ns16550a";
0076 reg = <0x70100000 0x20>;
0077 interrupts = <6>;
0078 clocks = <&ahb_clk>;
0079 reg-io-width = <4>;
0080 reg-shift = <2>;
0081
0082 status = "disabled";
0083 };
0084
0085 uart2: serial@70100800 {
0086 pinctrl-0 = <&uart2_pins>;
0087 pinctrl-names = "default";
0088 compatible = "ns16550a";
0089 reg = <0x70100800 0x20>;
0090 interrupts = <7>;
0091 clocks = <&ahb_clk>;
0092 reg-io-width = <4>;
0093 reg-shift = <2>;
0094
0095 status = "disabled";
0096 };
0097
0098 gpio: pinctrl@71010038 {
0099 compatible = "mscc,jaguar2-pinctrl";
0100 reg = <0x71010038 0x90>;
0101 gpio-controller;
0102 #gpio-cells = <2>;
0103 gpio-ranges = <&gpio 0 0 64>;
0104
0105 uart_pins: uart-pins {
0106 pins = "GPIO_10", "GPIO_11";
0107 function = "uart";
0108 };
0109
0110 uart2_pins: uart2-pins {
0111 pins = "GPIO_24", "GPIO_25";
0112 function = "uart2";
0113 };
0114
0115 cs1_pins: cs1-pins {
0116 pins = "GPIO_16";
0117 function = "si";
0118 };
0119
0120 cs2_pins: cs2-pins {
0121 pins = "GPIO_17";
0122 function = "si";
0123 };
0124
0125 cs3_pins: cs3-pins {
0126 pins = "GPIO_18";
0127 function = "si";
0128 };
0129
0130 i2c_pins: i2c-pins {
0131 pins = "GPIO_14", "GPIO_15";
0132 function = "twi";
0133 };
0134
0135 i2c2_pins: i2c2-pins {
0136 pins = "GPIO_28", "GPIO_29";
0137 function = "twi2";
0138 };
0139 };
0140
0141 i2c0: i2c@70100400 {
0142 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
0143 status = "disabled";
0144 pinctrl-0 = <&i2c_pins>;
0145 pinctrl-names = "default";
0146 reg = <0x70100400 0x100>, <0x700001b8 0x8>;
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149 interrupts = <8>;
0150 clock-frequency = <100000>;
0151 clocks = <&ahb_clk>;
0152 };
0153
0154 i2c2: i2c@70100c00 {
0155 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
0156 status = "disabled";
0157 pinctrl-0 = <&i2c2_pins>;
0158 pinctrl-names = "default";
0159 reg = <0x70100c00 0x100>;
0160 #address-cells = <1>;
0161 #size-cells = <0>;
0162 interrupts = <8>;
0163 clock-frequency = <100000>;
0164 clocks = <&ahb_clk>;
0165 };
0166 };
0167 };
