OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /dts-v1/;
0004
0005 #include <dt-bindings/interrupt-controller/irq.h>
0006
0007 / {
0008 compatible = "loongson,loongson2k1000";
0009
0010 #address-cells = <2>;
0011 #size-cells = <2>;
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu0: cpu@0 {
0018 device_type = "cpu";
0019 compatible = "loongson,gs264";
0020 reg = <0x0>;
0021 #clock-cells = <1>;
0022 clocks = <&cpu_clk>;
0023 };
0024 };
0025
0026 memory@200000 {
0027 compatible = "memory";
0028 device_type = "memory";
0029 reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
0030 <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
0031 <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
0032 };
0033
0034 cpu_clk: cpu_clk {
0035 #clock-cells = <0>;
0036 compatible = "fixed-clock";
0037 clock-frequency = <800000000>;
0038 };
0039
0040 cpuintc: interrupt-controller {
0041 #address-cells = <0>;
0042 #interrupt-cells = <1>;
0043 interrupt-controller;
0044 compatible = "mti,cpu-interrupt-controller";
0045 };
0046
0047 package0: bus@10000000 {
0048 compatible = "simple-bus";
0049 #address-cells = <2>;
0050 #size-cells = <2>;
0051 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
0052 0 0x40000000 0 0x40000000 0 0x40000000
0053 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
0054
0055 pm: reset-controller@1fe07000 {
0056 compatible = "loongson,ls2k-pm";
0057 reg = <0 0x1fe07000 0 0x422>;
0058 };
0059
0060 liointc0: interrupt-controller@1fe11400 {
0061 compatible = "loongson,liointc-2.0";
0062 reg = <0 0x1fe11400 0 0x40>,
0063 <0 0x1fe11040 0 0x8>,
0064 <0 0x1fe11140 0 0x8>;
0065 reg-names = "main", "isr0", "isr1";
0066
0067 interrupt-controller;
0068 #interrupt-cells = <2>;
0069
0070 interrupt-parent = <&cpuintc>;
0071 interrupts = <2>;
0072 interrupt-names = "int0";
0073
0074 loongson,parent_int_map = <0xffffffff>, /* int0 */
0075 <0x00000000>, /* int1 */
0076 <0x00000000>, /* int2 */
0077 <0x00000000>; /* int3 */
0078 };
0079
0080 liointc1: interrupt-controller@1fe11440 {
0081 compatible = "loongson,liointc-2.0";
0082 reg = <0 0x1fe11440 0 0x40>,
0083 <0 0x1fe11048 0 0x8>,
0084 <0 0x1fe11148 0 0x8>;
0085 reg-names = "main", "isr0", "isr1";
0086
0087 interrupt-controller;
0088 #interrupt-cells = <2>;
0089
0090 interrupt-parent = <&cpuintc>;
0091 interrupts = <3>;
0092 interrupt-names = "int1";
0093
0094 loongson,parent_int_map = <0x00000000>, /* int0 */
0095 <0xffffffff>, /* int1 */
0096 <0x00000000>, /* int2 */
0097 <0x00000000>; /* int3 */
0098 };
0099
0100 uart0: serial@1fe00000 {
0101 compatible = "ns16550a";
0102 reg = <0 0x1fe00000 0 0x8>;
0103 clock-frequency = <125000000>;
0104 interrupt-parent = <&liointc0>;
0105 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
0106 no-loopback-test;
0107 };
0108
0109 pci@1a000000 {
0110 compatible = "loongson,ls2k-pci";
0111 device_type = "pci";
0112 #address-cells = <3>;
0113 #size-cells = <2>;
0114 #interrupt-cells = <2>;
0115
0116 reg = <0 0x1a000000 0 0x02000000>,
0117 <0xfe 0x00000000 0 0x20000000>;
0118
0119 ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>,
0120 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
0121
0122 gmac@3,0 {
0123 compatible = "pci0014,7a03.0",
0124 "pci0014,7a03",
0125 "pciclass0c0320",
0126 "pciclass0c03",
0127 "loongson, pci-gmac";
0128
0129 reg = <0x1800 0x0 0x0 0x0 0x0>;
0130 interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
0131 <13 IRQ_TYPE_LEVEL_LOW>;
0132 interrupt-names = "macirq", "eth_lpi";
0133 interrupt-parent = <&liointc0>;
0134 phy-mode = "rgmii";
0135 mdio {
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138 compatible = "snps,dwmac-mdio";
0139 phy0: ethernet-phy@0 {
0140 reg = <0>;
0141 };
0142 };
0143 };
0144
0145 gmac@3,1 {
0146 compatible = "pci0014,7a03.0",
0147 "pci0014,7a03",
0148 "pciclass0c0320",
0149 "pciclass0c03",
0150 "loongson, pci-gmac";
0151
0152 reg = <0x1900 0x0 0x0 0x0 0x0>;
0153 interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
0154 <15 IRQ_TYPE_LEVEL_LOW>;
0155 interrupt-names = "macirq", "eth_lpi";
0156 interrupt-parent = <&liointc0>;
0157 phy-mode = "rgmii";
0158 mdio {
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 compatible = "snps,dwmac-mdio";
0162 phy1: ethernet-phy@1 {
0163 reg = <0>;
0164 };
0165 };
0166 };
0167
0168 ehci@4,1 {
0169 compatible = "pci0014,7a14.0",
0170 "pci0014,7a14",
0171 "pciclass0c0320",
0172 "pciclass0c03";
0173
0174 reg = <0x2100 0x0 0x0 0x0 0x0>;
0175 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0176 interrupt-parent = <&liointc1>;
0177 };
0178
0179 ohci@4,2 {
0180 compatible = "pci0014,7a24.0",
0181 "pci0014,7a24",
0182 "pciclass0c0310",
0183 "pciclass0c03";
0184
0185 reg = <0x2200 0x0 0x0 0x0 0x0>;
0186 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0187 interrupt-parent = <&liointc1>;
0188 };
0189
0190 sata@8,0 {
0191 compatible = "pci0014,7a08.0",
0192 "pci0014,7a08",
0193 "pciclass010601",
0194 "pciclass0106";
0195
0196 reg = <0x4000 0x0 0x0 0x0 0x0>;
0197 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0198 interrupt-parent = <&liointc0>;
0199 };
0200
0201 pci_bridge@9,0 {
0202 compatible = "pci0014,7a19.0",
0203 "pci0014,7a19",
0204 "pciclass060400",
0205 "pciclass0604";
0206
0207 reg = <0x4800 0x0 0x0 0x0 0x0>;
0208 #interrupt-cells = <1>;
0209 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
0210 interrupt-parent = <&liointc1>;
0211 interrupt-map-mask = <0 0 0 0>;
0212 interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
0213 external-facing;
0214 };
0215
0216 pci_bridge@a,0 {
0217 compatible = "pci0014,7a09.0",
0218 "pci0014,7a09",
0219 "pciclass060400",
0220 "pciclass0604";
0221
0222 reg = <0x5000 0x0 0x0 0x0 0x0>;
0223 #interrupt-cells = <1>;
0224 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
0225 interrupt-parent = <&liointc1>;
0226 interrupt-map-mask = <0 0 0 0>;
0227 interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
0228 external-facing;
0229 };
0230
0231 pci_bridge@b,0 {
0232 compatible = "pci0014,7a09.0",
0233 "pci0014,7a09",
0234 "pciclass060400",
0235 "pciclass0604";
0236
0237 reg = <0x5800 0x0 0x0 0x0 0x0>;
0238 #interrupt-cells = <1>;
0239 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
0240 interrupt-parent = <&liointc1>;
0241 interrupt-map-mask = <0 0 0 0>;
0242 interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
0243 external-facing;
0244 };
0245
0246 pci_bridge@c,0 {
0247 compatible = "pci0014,7a09.0",
0248 "pci0014,7a09",
0249 "pciclass060400",
0250 "pciclass0604";
0251
0252 reg = <0x6000 0x0 0x0 0x0 0x0>;
0253 #interrupt-cells = <1>;
0254 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0255 interrupt-parent = <&liointc1>;
0256 interrupt-map-mask = <0 0 0 0>;
0257 interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
0258 external-facing;
0259 };
0260
0261 pci_bridge@d,0 {
0262 compatible = "pci0014,7a19.0",
0263 "pci0014,7a19",
0264 "pciclass060400",
0265 "pciclass0604";
0266
0267 reg = <0x6800 0x0 0x0 0x0 0x0>;
0268 #interrupt-cells = <1>;
0269 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0270 interrupt-parent = <&liointc1>;
0271 interrupt-map-mask = <0 0 0 0>;
0272 interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
0273 external-facing;
0274 };
0275
0276 pci_bridge@e,0 {
0277 compatible = "pci0014,7a09.0",
0278 "pci0014,7a09",
0279 "pciclass060400",
0280 "pciclass0604";
0281
0282 reg = <0x7000 0x0 0x0 0x0 0x0>;
0283 #interrupt-cells = <1>;
0284 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
0285 interrupt-parent = <&liointc1>;
0286 interrupt-map-mask = <0 0 0 0>;
0287 interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
0288 external-facing;
0289 };
0290
0291 };
0292 };
0293 };
0294
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