0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/ingenic,tcu.h>
0003 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
0004 #include <dt-bindings/dma/x1830-dma.h>
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 compatible = "ingenic,x1830";
0010
0011 cpus {
0012 #address-cells = <1>;
0013 #size-cells = <0>;
0014
0015 cpu0: cpu@0 {
0016 device_type = "cpu";
0017 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
0018 reg = <0>;
0019
0020 clocks = <&cgu X1830_CLK_CPU>;
0021 clock-names = "cpu";
0022 };
0023 };
0024
0025 cpuintc: interrupt-controller {
0026 #address-cells = <0>;
0027 #interrupt-cells = <1>;
0028 interrupt-controller;
0029 compatible = "mti,cpu-interrupt-controller";
0030 };
0031
0032 intc: interrupt-controller@10001000 {
0033 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
0034 reg = <0x10001000 0x50>;
0035
0036 interrupt-controller;
0037 #interrupt-cells = <1>;
0038
0039 interrupt-parent = <&cpuintc>;
0040 interrupts = <2>;
0041 };
0042
0043 exclk: ext {
0044 compatible = "fixed-clock";
0045 #clock-cells = <0>;
0046 };
0047
0048 rtclk: rtc {
0049 compatible = "fixed-clock";
0050 #clock-cells = <0>;
0051 clock-frequency = <32768>;
0052 };
0053
0054 cgu: x1830-cgu@10000000 {
0055 compatible = "ingenic,x1830-cgu", "simple-mfd";
0056 reg = <0x10000000 0x100>;
0057 #address-cells = <1>;
0058 #size-cells = <1>;
0059 ranges = <0x0 0x10000000 0x100>;
0060
0061 #clock-cells = <1>;
0062
0063 clocks = <&exclk>, <&rtclk>;
0064 clock-names = "ext", "rtc";
0065
0066 otg_phy: usb-phy@3c {
0067 compatible = "ingenic,x1830-phy";
0068 reg = <0x3c 0x10>;
0069
0070 clocks = <&cgu X1830_CLK_OTGPHY>;
0071
0072 #phy-cells = <0>;
0073
0074 status = "disabled";
0075 };
0076
0077 mac_phy_ctrl: mac-phy-ctrl@e8 {
0078 compatible = "syscon";
0079 reg = <0xe8 0x4>;
0080 };
0081 };
0082
0083 ost: timer@12000000 {
0084 compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
0085 reg = <0x12000000 0x3c>;
0086
0087 #clock-cells = <1>;
0088
0089 clocks = <&cgu X1830_CLK_OST>;
0090 clock-names = "ost";
0091
0092 interrupt-parent = <&cpuintc>;
0093 interrupts = <4>;
0094 };
0095
0096 tcu: timer@10002000 {
0097 compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
0098 reg = <0x10002000 0x1000>;
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 ranges = <0x0 0x10002000 0x1000>;
0102
0103 #clock-cells = <1>;
0104
0105 clocks = <&cgu X1830_CLK_RTCLK>,
0106 <&cgu X1830_CLK_EXCLK>,
0107 <&cgu X1830_CLK_PCLK>,
0108 <&cgu X1830_CLK_TCU>;
0109 clock-names = "rtc", "ext", "pclk", "tcu";
0110
0111 interrupt-controller;
0112 #interrupt-cells = <1>;
0113
0114 interrupt-parent = <&intc>;
0115 interrupts = <27 26 25>;
0116
0117 wdt: watchdog@0 {
0118 compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
0119 reg = <0x0 0x10>;
0120
0121 clocks = <&tcu TCU_CLK_WDT>;
0122 clock-names = "wdt";
0123 };
0124
0125 pwm: pwm@40 {
0126 compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm";
0127 reg = <0x40 0x80>;
0128
0129 #pwm-cells = <3>;
0130
0131 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
0132 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
0133 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
0134 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
0135 clock-names = "timer0", "timer1", "timer2", "timer3",
0136 "timer4", "timer5", "timer6", "timer7";
0137 };
0138 };
0139
0140 rtc: rtc@10003000 {
0141 compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
0142 reg = <0x10003000 0x4c>;
0143
0144 interrupt-parent = <&intc>;
0145 interrupts = <32>;
0146
0147 clocks = <&cgu X1830_CLK_RTCLK>;
0148 clock-names = "rtc";
0149 };
0150
0151 pinctrl: pin-controller@10010000 {
0152 compatible = "ingenic,x1830-pinctrl";
0153 reg = <0x10010000 0x800>;
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156
0157 gpa: gpio@0 {
0158 compatible = "ingenic,x1830-gpio";
0159 reg = <0>;
0160
0161 gpio-controller;
0162 gpio-ranges = <&pinctrl 0 0 32>;
0163 #gpio-cells = <2>;
0164
0165 interrupt-controller;
0166 #interrupt-cells = <2>;
0167
0168 interrupt-parent = <&intc>;
0169 interrupts = <17>;
0170 };
0171
0172 gpb: gpio@1 {
0173 compatible = "ingenic,x1830-gpio";
0174 reg = <1>;
0175
0176 gpio-controller;
0177 gpio-ranges = <&pinctrl 0 32 32>;
0178 #gpio-cells = <2>;
0179
0180 interrupt-controller;
0181 #interrupt-cells = <2>;
0182
0183 interrupt-parent = <&intc>;
0184 interrupts = <16>;
0185 };
0186
0187 gpc: gpio@2 {
0188 compatible = "ingenic,x1830-gpio";
0189 reg = <2>;
0190
0191 gpio-controller;
0192 gpio-ranges = <&pinctrl 0 64 32>;
0193 #gpio-cells = <2>;
0194
0195 interrupt-controller;
0196 #interrupt-cells = <2>;
0197
0198 interrupt-parent = <&intc>;
0199 interrupts = <15>;
0200 };
0201
0202 gpd: gpio@3 {
0203 compatible = "ingenic,x1830-gpio";
0204 reg = <3>;
0205
0206 gpio-controller;
0207 gpio-ranges = <&pinctrl 0 96 32>;
0208 #gpio-cells = <2>;
0209
0210 interrupt-controller;
0211 #interrupt-cells = <2>;
0212
0213 interrupt-parent = <&intc>;
0214 interrupts = <14>;
0215 };
0216 };
0217
0218 uart0: serial@10030000 {
0219 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
0220 reg = <0x10030000 0x100>;
0221
0222 interrupt-parent = <&intc>;
0223 interrupts = <51>;
0224
0225 clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
0226 clock-names = "baud", "module";
0227
0228 status = "disabled";
0229 };
0230
0231 uart1: serial@10031000 {
0232 compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
0233 reg = <0x10031000 0x100>;
0234
0235 interrupt-parent = <&intc>;
0236 interrupts = <50>;
0237
0238 clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
0239 clock-names = "baud", "module";
0240
0241 status = "disabled";
0242 };
0243
0244 ssi0: spi@10043000 {
0245 compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
0246 reg = <0x10043000 0x20>;
0247 #address-cells = <1>;
0248 #size-cells = <0>;
0249
0250 interrupt-parent = <&intc>;
0251 interrupts = <9>;
0252
0253 clocks = <&cgu X1830_CLK_SSI0>;
0254 clock-names = "spi";
0255
0256 dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
0257 <&pdma X1830_DMA_SSI0_TX 0xffffffff>;
0258 dma-names = "rx", "tx";
0259
0260 status = "disabled";
0261 };
0262
0263 ssi1: spi@10044000 {
0264 compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
0265 reg = <0x10044000 0x20>;
0266 #address-cells = <1>;
0267 #size-cells = <0>;
0268
0269 interrupt-parent = <&intc>;
0270 interrupts = <8>;
0271
0272 clocks = <&cgu X1830_CLK_SSI1>;
0273 clock-names = "spi";
0274
0275 dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
0276 <&pdma X1830_DMA_SSI1_TX 0xffffffff>;
0277 dma-names = "rx", "tx";
0278
0279 status = "disabled";
0280 };
0281
0282 i2c0: i2c-controller@10050000 {
0283 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
0284 reg = <0x10050000 0x1000>;
0285 #address-cells = <1>;
0286 #size-cells = <0>;
0287
0288 interrupt-parent = <&intc>;
0289 interrupts = <60>;
0290
0291 clocks = <&cgu X1830_CLK_SMB0>;
0292
0293 status = "disabled";
0294 };
0295
0296 i2c1: i2c-controller@10051000 {
0297 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
0298 reg = <0x10051000 0x1000>;
0299 #address-cells = <1>;
0300 #size-cells = <0>;
0301
0302 interrupt-parent = <&intc>;
0303 interrupts = <59>;
0304
0305 clocks = <&cgu X1830_CLK_SMB1>;
0306
0307 status = "disabled";
0308 };
0309
0310 i2c2: i2c-controller@10052000 {
0311 compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
0312 reg = <0x10052000 0x1000>;
0313 #address-cells = <1>;
0314 #size-cells = <0>;
0315
0316 interrupt-parent = <&intc>;
0317 interrupts = <58>;
0318
0319 clocks = <&cgu X1830_CLK_SMB2>;
0320
0321 status = "disabled";
0322 };
0323
0324 dtrng: trng@10072000 {
0325 compatible = "ingenic,x1830-dtrng";
0326 reg = <0x10072000 0xc>;
0327
0328 clocks = <&cgu X1830_CLK_DTRNG>;
0329
0330 status = "disabled";
0331 };
0332
0333 pdma: dma-controller@13420000 {
0334 compatible = "ingenic,x1830-dma";
0335 reg = <0x13420000 0x400>, <0x13421000 0x40>;
0336
0337 #dma-cells = <2>;
0338
0339 interrupt-parent = <&intc>;
0340 interrupts = <10>;
0341
0342 clocks = <&cgu X1830_CLK_PDMA>;
0343 };
0344
0345 msc0: mmc@13450000 {
0346 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
0347 reg = <0x13450000 0x1000>;
0348
0349 interrupt-parent = <&intc>;
0350 interrupts = <37>;
0351
0352 clocks = <&cgu X1830_CLK_MSC0>;
0353 clock-names = "mmc";
0354
0355 cap-sd-highspeed;
0356 cap-mmc-highspeed;
0357 cap-sdio-irq;
0358
0359 dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
0360 <&pdma X1830_DMA_MSC0_TX 0xffffffff>;
0361 dma-names = "rx", "tx";
0362
0363 status = "disabled";
0364 };
0365
0366 msc1: mmc@13460000 {
0367 compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
0368 reg = <0x13460000 0x1000>;
0369
0370 interrupt-parent = <&intc>;
0371 interrupts = <36>;
0372
0373 clocks = <&cgu X1830_CLK_MSC1>;
0374 clock-names = "mmc";
0375
0376 cap-sd-highspeed;
0377 cap-mmc-highspeed;
0378 cap-sdio-irq;
0379
0380 dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
0381 <&pdma X1830_DMA_MSC1_TX 0xffffffff>;
0382 dma-names = "rx", "tx";
0383
0384 status = "disabled";
0385 };
0386
0387 mac: ethernet@134b0000 {
0388 compatible = "ingenic,x1830-mac", "snps,dwmac";
0389 reg = <0x134b0000 0x2000>;
0390
0391 interrupt-parent = <&intc>;
0392 interrupts = <55>;
0393 interrupt-names = "macirq";
0394
0395 clocks = <&cgu X1830_CLK_MAC>;
0396 clock-names = "stmmaceth";
0397
0398 mode-reg = <&mac_phy_ctrl>;
0399
0400 status = "disabled";
0401
0402 mdio: mdio {
0403 compatible = "snps,dwmac-mdio";
0404 #address-cells = <1>;
0405 #size-cells = <0>;
0406
0407 status = "disabled";
0408 };
0409 };
0410
0411 otg: usb@13500000 {
0412 compatible = "ingenic,x1830-otg";
0413 reg = <0x13500000 0x40000>;
0414
0415 interrupt-parent = <&intc>;
0416 interrupts = <21>;
0417
0418 clocks = <&cgu X1830_CLK_OTG>;
0419 clock-names = "otg";
0420
0421 phys = <&otg_phy>;
0422 phy-names = "usb2-phy";
0423
0424 g-rx-fifo-size = <768>;
0425 g-np-tx-fifo-size = <256>;
0426 g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
0427
0428 status = "disabled";
0429 };
0430 };
