0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
0003 #include <dt-bindings/clock/ingenic,tcu.h>
0004
0005 / {
0006 #address-cells = <1>;
0007 #size-cells = <1>;
0008 compatible = "ingenic,jz4740";
0009
0010 cpus {
0011 #address-cells = <1>;
0012 #size-cells = <0>;
0013
0014 cpu0: cpu@0 {
0015 device_type = "cpu";
0016 compatible = "ingenic,xburst-mxu1.0";
0017 reg = <0>;
0018
0019 clocks = <&cgu JZ4740_CLK_CCLK>;
0020 clock-names = "cpu";
0021 };
0022 };
0023
0024 cpuintc: interrupt-controller {
0025 #address-cells = <0>;
0026 #interrupt-cells = <1>;
0027 interrupt-controller;
0028 compatible = "mti,cpu-interrupt-controller";
0029 };
0030
0031 intc: interrupt-controller@10001000 {
0032 compatible = "ingenic,jz4740-intc";
0033 reg = <0x10001000 0x14>;
0034
0035 interrupt-controller;
0036 #interrupt-cells = <1>;
0037
0038 interrupt-parent = <&cpuintc>;
0039 interrupts = <2>;
0040 };
0041
0042 ext: ext {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 };
0046
0047 rtc: rtc {
0048 compatible = "fixed-clock";
0049 #clock-cells = <0>;
0050 clock-frequency = <32768>;
0051 };
0052
0053 cgu: jz4740-cgu@10000000 {
0054 compatible = "ingenic,jz4740-cgu";
0055 reg = <0x10000000 0x100>;
0056
0057 clocks = <&ext>, <&rtc>;
0058 clock-names = "ext", "rtc";
0059
0060 #clock-cells = <1>;
0061 };
0062
0063 tcu: timer@10002000 {
0064 compatible = "ingenic,jz4740-tcu", "simple-mfd";
0065 reg = <0x10002000 0x1000>;
0066 #address-cells = <1>;
0067 #size-cells = <1>;
0068 ranges = <0x0 0x10002000 0x1000>;
0069
0070 #clock-cells = <1>;
0071
0072 clocks = <&cgu JZ4740_CLK_RTC>,
0073 <&cgu JZ4740_CLK_EXT>,
0074 <&cgu JZ4740_CLK_PCLK>,
0075 <&cgu JZ4740_CLK_TCU>;
0076 clock-names = "rtc", "ext", "pclk", "tcu";
0077
0078 interrupt-controller;
0079 #interrupt-cells = <1>;
0080
0081 interrupt-parent = <&intc>;
0082 interrupts = <23 22 21>;
0083
0084 watchdog: watchdog@0 {
0085 compatible = "ingenic,jz4740-watchdog";
0086 reg = <0x0 0xc>;
0087
0088 clocks = <&tcu TCU_CLK_WDT>;
0089 clock-names = "wdt";
0090 };
0091
0092 pwm: pwm@40 {
0093 compatible = "ingenic,jz4740-pwm";
0094 reg = <0x40 0x80>;
0095
0096 #pwm-cells = <3>;
0097
0098 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
0099 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
0100 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
0101 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
0102 clock-names = "timer0", "timer1", "timer2", "timer3",
0103 "timer4", "timer5", "timer6", "timer7";
0104 };
0105 };
0106
0107 rtc_dev: rtc@10003000 {
0108 compatible = "ingenic,jz4740-rtc";
0109 reg = <0x10003000 0x40>;
0110
0111 interrupt-parent = <&intc>;
0112 interrupts = <15>;
0113
0114 clocks = <&cgu JZ4740_CLK_RTC>;
0115 clock-names = "rtc";
0116 };
0117
0118 pinctrl: pin-controller@10010000 {
0119 compatible = "ingenic,jz4740-pinctrl";
0120 reg = <0x10010000 0x400>;
0121
0122 #address-cells = <1>;
0123 #size-cells = <0>;
0124
0125 gpa: gpio@0 {
0126 compatible = "ingenic,jz4740-gpio";
0127 reg = <0>;
0128
0129 gpio-controller;
0130 gpio-ranges = <&pinctrl 0 0 32>;
0131 #gpio-cells = <2>;
0132
0133 interrupt-controller;
0134 #interrupt-cells = <2>;
0135
0136 interrupt-parent = <&intc>;
0137 interrupts = <28>;
0138 };
0139
0140 gpb: gpio@1 {
0141 compatible = "ingenic,jz4740-gpio";
0142 reg = <1>;
0143
0144 gpio-controller;
0145 gpio-ranges = <&pinctrl 0 32 32>;
0146 #gpio-cells = <2>;
0147
0148 interrupt-controller;
0149 #interrupt-cells = <2>;
0150
0151 interrupt-parent = <&intc>;
0152 interrupts = <27>;
0153 };
0154
0155 gpc: gpio@2 {
0156 compatible = "ingenic,jz4740-gpio";
0157 reg = <2>;
0158
0159 gpio-controller;
0160 gpio-ranges = <&pinctrl 0 64 32>;
0161 #gpio-cells = <2>;
0162
0163 interrupt-controller;
0164 #interrupt-cells = <2>;
0165
0166 interrupt-parent = <&intc>;
0167 interrupts = <26>;
0168 };
0169
0170 gpd: gpio@3 {
0171 compatible = "ingenic,jz4740-gpio";
0172 reg = <3>;
0173
0174 gpio-controller;
0175 gpio-ranges = <&pinctrl 0 96 32>;
0176 #gpio-cells = <2>;
0177
0178 interrupt-controller;
0179 #interrupt-cells = <2>;
0180
0181 interrupt-parent = <&intc>;
0182 interrupts = <25>;
0183 };
0184 };
0185
0186 aic: audio-controller@10020000 {
0187 compatible = "ingenic,jz4740-i2s";
0188 reg = <0x10020000 0x38>;
0189
0190 #sound-dai-cells = <0>;
0191
0192 interrupt-parent = <&intc>;
0193 interrupts = <18>;
0194
0195 clocks = <&cgu JZ4740_CLK_AIC>,
0196 <&cgu JZ4740_CLK_I2S>,
0197 <&cgu JZ4740_CLK_EXT>,
0198 <&cgu JZ4740_CLK_PLL_HALF>;
0199 clock-names = "aic", "i2s", "ext", "pll half";
0200
0201 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
0202 dma-names = "rx", "tx";
0203 };
0204
0205 codec: audio-codec@100200a4 {
0206 compatible = "ingenic,jz4740-codec";
0207 reg = <0x10020080 0x8>;
0208
0209 #sound-dai-cells = <0>;
0210
0211 clocks = <&cgu JZ4740_CLK_AIC>;
0212 clock-names = "aic";
0213 };
0214
0215 mmc: mmc@10021000 {
0216 compatible = "ingenic,jz4740-mmc";
0217 reg = <0x10021000 0x1000>;
0218
0219 clocks = <&cgu JZ4740_CLK_MMC>;
0220 clock-names = "mmc";
0221
0222 interrupt-parent = <&intc>;
0223 interrupts = <14>;
0224
0225 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
0226 dma-names = "rx", "tx";
0227
0228 cap-sd-highspeed;
0229 cap-mmc-highspeed;
0230 cap-sdio-irq;
0231 };
0232
0233 uart0: serial@10030000 {
0234 compatible = "ingenic,jz4740-uart";
0235 reg = <0x10030000 0x100>;
0236
0237 interrupt-parent = <&intc>;
0238 interrupts = <9>;
0239
0240 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
0241 clock-names = "baud", "module";
0242 };
0243
0244 uart1: serial@10031000 {
0245 compatible = "ingenic,jz4740-uart";
0246 reg = <0x10031000 0x100>;
0247
0248 interrupt-parent = <&intc>;
0249 interrupts = <8>;
0250
0251 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
0252 clock-names = "baud", "module";
0253 };
0254
0255 adc: adc@10070000 {
0256 compatible = "ingenic,jz4740-adc";
0257 reg = <0x10070000 0x30>;
0258 #io-channel-cells = <1>;
0259
0260 clocks = <&cgu JZ4740_CLK_ADC>;
0261 clock-names = "adc";
0262
0263 interrupt-parent = <&intc>;
0264 interrupts = <12>;
0265 };
0266
0267 nemc: memory-controller@13010000 {
0268 compatible = "ingenic,jz4740-nemc";
0269 reg = <0x13010000 0x54>;
0270 #address-cells = <2>;
0271 #size-cells = <1>;
0272 ranges = <1 0 0x18000000 0x4000000>,
0273 <2 0 0x14000000 0x4000000>,
0274 <3 0 0x0c000000 0x4000000>,
0275 <4 0 0x08000000 0x4000000>;
0276
0277 clocks = <&cgu JZ4740_CLK_MCLK>;
0278 };
0279
0280 ecc: ecc-controller@13010100 {
0281 compatible = "ingenic,jz4740-ecc";
0282 reg = <0x13010100 0x2C>;
0283
0284 clocks = <&cgu JZ4740_CLK_MCLK>;
0285 };
0286
0287 dmac: dma-controller@13020000 {
0288 compatible = "ingenic,jz4740-dma";
0289 reg = <0x13020000 0xbc>, <0x13020300 0x14>;
0290 #dma-cells = <2>;
0291
0292 interrupt-parent = <&intc>;
0293 interrupts = <20>;
0294
0295 clocks = <&cgu JZ4740_CLK_DMA>;
0296 };
0297
0298 uhc: usb@13030000 {
0299 compatible = "ingenic,jz4740-ohci", "generic-ohci";
0300 reg = <0x13030000 0x1000>;
0301
0302 clocks = <&cgu JZ4740_CLK_UHC>;
0303 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
0304 assigned-clock-rates = <48000000>;
0305
0306 interrupt-parent = <&intc>;
0307 interrupts = <3>;
0308
0309 status = "disabled";
0310 };
0311
0312 udc: usb@13040000 {
0313 compatible = "ingenic,jz4740-musb";
0314 reg = <0x13040000 0x10000>;
0315
0316 interrupt-parent = <&intc>;
0317 interrupts = <24>;
0318 interrupt-names = "mc";
0319
0320 clocks = <&cgu JZ4740_CLK_UDC>;
0321 clock-names = "udc";
0322 };
0323
0324 lcd: lcd-controller@13050000 {
0325 compatible = "ingenic,jz4740-lcd";
0326 reg = <0x13050000 0x60>; /* LCDCMD1+4 */
0327
0328 interrupt-parent = <&intc>;
0329 interrupts = <30>;
0330
0331 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
0332 clock-names = "lcd_pclk", "lcd";
0333 };
0334 };
