0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
0003 #include <dt-bindings/clock/ingenic,tcu.h>
0004
0005 / {
0006 #address-cells = <1>;
0007 #size-cells = <1>;
0008 compatible = "ingenic,jz4725b";
0009
0010 cpus {
0011 #address-cells = <1>;
0012 #size-cells = <0>;
0013
0014 cpu0: cpu@0 {
0015 device_type = "cpu";
0016 compatible = "ingenic,xburst-mxu1.0";
0017 reg = <0>;
0018
0019 clocks = <&cgu JZ4725B_CLK_CCLK>;
0020 clock-names = "cpu";
0021 };
0022 };
0023
0024 cpuintc: interrupt-controller {
0025 #address-cells = <0>;
0026 #interrupt-cells = <1>;
0027 interrupt-controller;
0028 compatible = "mti,cpu-interrupt-controller";
0029 };
0030
0031 intc: interrupt-controller@10001000 {
0032 compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
0033 reg = <0x10001000 0x14>;
0034
0035 interrupt-controller;
0036 #interrupt-cells = <1>;
0037
0038 interrupt-parent = <&cpuintc>;
0039 interrupts = <2>;
0040 };
0041
0042 ext: ext {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 };
0046
0047 osc32k: osc32k {
0048 compatible = "fixed-clock";
0049 #clock-cells = <0>;
0050 clock-frequency = <32768>;
0051 };
0052
0053 cgu: clock-controller@10000000 {
0054 compatible = "ingenic,jz4725b-cgu";
0055 reg = <0x10000000 0x100>;
0056
0057 clocks = <&ext>, <&osc32k>;
0058 clock-names = "ext", "osc32k";
0059
0060 #clock-cells = <1>;
0061 };
0062
0063 tcu: timer@10002000 {
0064 compatible = "ingenic,jz4725b-tcu", "simple-mfd";
0065 reg = <0x10002000 0x1000>;
0066 #address-cells = <1>;
0067 #size-cells = <1>;
0068 ranges = <0x0 0x10002000 0x1000>;
0069
0070 #clock-cells = <1>;
0071
0072 clocks = <&cgu JZ4725B_CLK_RTC>,
0073 <&cgu JZ4725B_CLK_EXT>,
0074 <&cgu JZ4725B_CLK_PCLK>,
0075 <&cgu JZ4725B_CLK_TCU>;
0076 clock-names = "rtc", "ext", "pclk", "tcu";
0077
0078 interrupt-controller;
0079 #interrupt-cells = <1>;
0080
0081 interrupt-parent = <&intc>;
0082 interrupts = <23>, <22>, <21>;
0083
0084 watchdog: watchdog@0 {
0085 compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
0086 reg = <0x0 0xc>;
0087
0088 clocks = <&tcu TCU_CLK_WDT>;
0089 clock-names = "wdt";
0090 };
0091
0092 pwm: pwm@60 {
0093 compatible = "ingenic,jz4725b-pwm";
0094 reg = <0x60 0x40>;
0095
0096 #pwm-cells = <3>;
0097
0098 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
0099 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
0100 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
0101 clock-names = "timer0", "timer1", "timer2",
0102 "timer3", "timer4", "timer5";
0103 };
0104
0105 ost: timer@e0 {
0106 compatible = "ingenic,jz4725b-ost";
0107 reg = <0xe0 0x20>;
0108
0109 clocks = <&tcu TCU_CLK_OST>;
0110 clock-names = "ost";
0111
0112 interrupts = <15>;
0113 };
0114 };
0115
0116 rtc_dev: rtc@10003000 {
0117 compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
0118 reg = <0x10003000 0x40>;
0119
0120 interrupt-parent = <&intc>;
0121 interrupts = <6>;
0122
0123 clocks = <&cgu JZ4725B_CLK_RTC>;
0124 clock-names = "rtc";
0125 };
0126
0127 pinctrl: pinctrl@10010000 {
0128 compatible = "ingenic,jz4725b-pinctrl";
0129 reg = <0x10010000 0x400>;
0130
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133
0134 gpa: gpio@0 {
0135 compatible = "ingenic,jz4725b-gpio";
0136 reg = <0>;
0137
0138 gpio-controller;
0139 gpio-ranges = <&pinctrl 0 0 32>;
0140 #gpio-cells = <2>;
0141
0142 interrupt-controller;
0143 #interrupt-cells = <2>;
0144
0145 interrupt-parent = <&intc>;
0146 interrupts = <16>;
0147 };
0148
0149 gpb: gpio@1 {
0150 compatible = "ingenic,jz4725b-gpio";
0151 reg = <1>;
0152
0153 gpio-controller;
0154 gpio-ranges = <&pinctrl 0 32 32>;
0155 #gpio-cells = <2>;
0156
0157 interrupt-controller;
0158 #interrupt-cells = <2>;
0159
0160 interrupt-parent = <&intc>;
0161 interrupts = <15>;
0162 };
0163
0164 gpc: gpio@2 {
0165 compatible = "ingenic,jz4725b-gpio";
0166 reg = <2>;
0167
0168 gpio-controller;
0169 gpio-ranges = <&pinctrl 0 64 32>;
0170 #gpio-cells = <2>;
0171
0172 interrupt-controller;
0173 #interrupt-cells = <2>;
0174
0175 interrupt-parent = <&intc>;
0176 interrupts = <14>;
0177 };
0178
0179 gpd: gpio@3 {
0180 compatible = "ingenic,jz4725b-gpio";
0181 reg = <3>;
0182
0183 gpio-controller;
0184 gpio-ranges = <&pinctrl 0 96 32>;
0185 #gpio-cells = <2>;
0186
0187 interrupt-controller;
0188 #interrupt-cells = <2>;
0189
0190 interrupt-parent = <&intc>;
0191 interrupts = <13>;
0192 };
0193 };
0194
0195 aic: audio-controller@10020000 {
0196 compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
0197 reg = <0x10020000 0x38>;
0198
0199 #sound-dai-cells = <0>;
0200
0201 clocks = <&cgu JZ4725B_CLK_AIC>,
0202 <&cgu JZ4725B_CLK_I2S>,
0203 <&cgu JZ4725B_CLK_EXT>,
0204 <&cgu JZ4725B_CLK_PLL_HALF>;
0205 clock-names = "aic", "i2s", "ext", "pll half";
0206
0207 interrupt-parent = <&intc>;
0208 interrupts = <10>;
0209
0210 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
0211 dma-names = "rx", "tx";
0212 };
0213
0214 codec: audio-codec@100200a4 {
0215 compatible = "ingenic,jz4725b-codec";
0216 reg = <0x100200a4 0x8>;
0217
0218 #sound-dai-cells = <0>;
0219
0220 clocks = <&cgu JZ4725B_CLK_AIC>;
0221 clock-names = "aic";
0222 };
0223
0224 mmc0: mmc@10021000 {
0225 compatible = "ingenic,jz4725b-mmc";
0226 reg = <0x10021000 0x1000>;
0227
0228 clocks = <&cgu JZ4725B_CLK_MMC0>;
0229 clock-names = "mmc";
0230
0231 interrupt-parent = <&intc>;
0232 interrupts = <25>;
0233
0234 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
0235 dma-names = "rx", "tx";
0236
0237 cap-sd-highspeed;
0238 cap-mmc-highspeed;
0239 cap-sdio-irq;
0240 };
0241
0242 mmc1: mmc@10022000 {
0243 compatible = "ingenic,jz4725b-mmc";
0244 reg = <0x10022000 0x1000>;
0245
0246 clocks = <&cgu JZ4725B_CLK_MMC1>;
0247 clock-names = "mmc";
0248
0249 interrupt-parent = <&intc>;
0250 interrupts = <24>;
0251
0252 dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
0253 dma-names = "rx", "tx";
0254
0255 cap-sd-highspeed;
0256 cap-mmc-highspeed;
0257 cap-sdio-irq;
0258 };
0259
0260 uart: serial@10030000 {
0261 compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
0262 reg = <0x10030000 0x100>;
0263
0264 interrupt-parent = <&intc>;
0265 interrupts = <9>;
0266
0267 clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
0268 clock-names = "baud", "module";
0269 };
0270
0271 adc: adc@10070000 {
0272 compatible = "ingenic,jz4725b-adc";
0273 #io-channel-cells = <1>;
0274
0275 reg = <0x10070000 0x30>;
0276 #address-cells = <1>;
0277 #size-cells = <1>;
0278 ranges = <0x0 0x10070000 0x30>;
0279
0280 clocks = <&cgu JZ4725B_CLK_ADC>;
0281 clock-names = "adc";
0282
0283 interrupt-parent = <&intc>;
0284 interrupts = <18>;
0285 };
0286
0287 nemc: memory-controller@13010000 {
0288 compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
0289 reg = <0x13010000 0x10000>;
0290 #address-cells = <2>;
0291 #size-cells = <1>;
0292 ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
0293 <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
0294
0295 clocks = <&cgu JZ4725B_CLK_MCLK>;
0296 };
0297
0298 dmac: dma-controller@13020000 {
0299 compatible = "ingenic,jz4725b-dma";
0300 reg = <0x13020000 0xd8>, <0x13020300 0x14>;
0301
0302 #dma-cells = <2>;
0303
0304 interrupt-parent = <&intc>;
0305 interrupts = <29>;
0306
0307 clocks = <&cgu JZ4725B_CLK_DMA>;
0308 };
0309
0310 udc: usb@13040000 {
0311 compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
0312 reg = <0x13040000 0x10000>;
0313
0314 interrupt-parent = <&intc>;
0315 interrupts = <27>;
0316 interrupt-names = "mc";
0317
0318 clocks = <&cgu JZ4725B_CLK_UDC>;
0319 clock-names = "udc";
0320 };
0321
0322 lcd: lcd-controller@13050000 {
0323 compatible = "ingenic,jz4725b-lcd";
0324 reg = <0x13050000 0x130>; /* tbc */
0325
0326 interrupt-parent = <&intc>;
0327 interrupts = <31>;
0328
0329 clocks = <&cgu JZ4725B_CLK_LCD>;
0330 clock-names = "lcd_pclk";
0331
0332 lcd_ports: ports {
0333 #address-cells = <1>;
0334 #size-cells = <0>;
0335
0336 port@8 {
0337 reg = <8>;
0338
0339 ipu_output: endpoint {
0340 remote-endpoint = <&ipu_input>;
0341 };
0342 };
0343 };
0344 };
0345
0346 ipu: ipu@13080000 {
0347 compatible = "ingenic,jz4725b-ipu";
0348 reg = <0x13080000 0x64>;
0349
0350 interrupt-parent = <&intc>;
0351 interrupts = <30>;
0352
0353 clocks = <&cgu JZ4725B_CLK_IPU>;
0354 clock-names = "ipu";
0355
0356 port {
0357 ipu_input: endpoint {
0358 remote-endpoint = <&ipu_output>;
0359 };
0360 };
0361 };
0362
0363 bch: ecc-controller@130d0000 {
0364 compatible = "ingenic,jz4725b-bch";
0365 reg = <0x130d0000 0x44>;
0366
0367 clocks = <&cgu JZ4725B_CLK_BCH>;
0368 };
0369
0370 rom: memory@1fc00000 {
0371 compatible = "mtd-rom";
0372 probe-type = "map_rom";
0373 reg = <0x1fc00000 0x2000>;
0374
0375 bank-width = <4>;
0376 device-width = <1>;
0377 };
0378 };
