0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
0004 * Copyright (C) 2015 Google, Inc.
0005 */
0006
0007 #include <dt-bindings/clock/pistachio-clk.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/mips-gic.h>
0011 #include <dt-bindings/reset/pistachio-resets.h>
0012
0013 / {
0014 compatible = "img,pistachio";
0015
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018
0019 interrupt-parent = <&gic>;
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu0: cpu@0 {
0026 device_type = "cpu";
0027 compatible = "mti,interaptiv";
0028 reg = <0>;
0029 clocks = <&clk_core CLK_MIPS_PLL>;
0030 clock-names = "cpu";
0031 clock-latency = <1000>;
0032 operating-points = <
0033 /* kHz uV(dummy) */
0034 546000 1150000
0035 520000 1100000
0036 494000 1000000
0037 468000 950000
0038 442000 900000
0039 416000 800000
0040 >;
0041 };
0042 };
0043
0044 i2c0: i2c@18100000 {
0045 compatible = "img,scb-i2c";
0046 reg = <0x18100000 0x200>;
0047 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
0048 clocks = <&clk_periph PERIPH_CLK_I2C0>,
0049 <&cr_periph SYS_CLK_I2C0>;
0050 clock-names = "scb", "sys";
0051 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
0052 <&clk_periph PERIPH_CLK_I2C0_DIV>;
0053 assigned-clock-rates = <100000000>, <33333334>;
0054 status = "disabled";
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&i2c0_pins>;
0057
0058 #address-cells = <1>;
0059 #size-cells = <0>;
0060 };
0061
0062 i2c1: i2c@18100200 {
0063 compatible = "img,scb-i2c";
0064 reg = <0x18100200 0x200>;
0065 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
0066 clocks = <&clk_periph PERIPH_CLK_I2C1>,
0067 <&cr_periph SYS_CLK_I2C1>;
0068 clock-names = "scb", "sys";
0069 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
0070 <&clk_periph PERIPH_CLK_I2C1_DIV>;
0071 assigned-clock-rates = <100000000>, <33333334>;
0072 status = "disabled";
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&i2c1_pins>;
0075
0076 #address-cells = <1>;
0077 #size-cells = <0>;
0078 };
0079
0080 i2c2: i2c@18100400 {
0081 compatible = "img,scb-i2c";
0082 reg = <0x18100400 0x200>;
0083 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
0084 clocks = <&clk_periph PERIPH_CLK_I2C2>,
0085 <&cr_periph SYS_CLK_I2C2>;
0086 clock-names = "scb", "sys";
0087 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
0088 <&clk_periph PERIPH_CLK_I2C2_DIV>;
0089 assigned-clock-rates = <100000000>, <33333334>;
0090 status = "disabled";
0091 pinctrl-names = "default";
0092 pinctrl-0 = <&i2c2_pins>;
0093
0094 #address-cells = <1>;
0095 #size-cells = <0>;
0096 };
0097
0098 i2c3: i2c@18100600 {
0099 compatible = "img,scb-i2c";
0100 reg = <0x18100600 0x200>;
0101 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
0102 clocks = <&clk_periph PERIPH_CLK_I2C3>,
0103 <&cr_periph SYS_CLK_I2C3>;
0104 clock-names = "scb", "sys";
0105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
0106 <&clk_periph PERIPH_CLK_I2C3_DIV>;
0107 assigned-clock-rates = <100000000>, <33333334>;
0108 status = "disabled";
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&i2c3_pins>;
0111
0112 #address-cells = <1>;
0113 #size-cells = <0>;
0114 };
0115
0116 i2s_in: i2s-in@18100800 {
0117 compatible = "img,i2s-in";
0118 reg = <0x18100800 0x200>;
0119 interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
0120 dmas = <&mdc 30 0xffffffff 0>;
0121 dma-names = "rx";
0122 clocks = <&cr_periph SYS_CLK_I2S_IN>;
0123 clock-names = "sys";
0124 img,i2s-channels = <6>;
0125 pinctrl-names = "default";
0126 pinctrl-0 = <&i2s_in_pins>;
0127 status = "disabled";
0128
0129 #sound-dai-cells = <0>;
0130 };
0131
0132 i2s_out: i2s-out@18100a00 {
0133 compatible = "img,i2s-out";
0134 reg = <0x18100a00 0x200>;
0135 interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
0136 dmas = <&mdc 23 0xffffffff 0>;
0137 dma-names = "tx";
0138 clocks = <&cr_periph SYS_CLK_I2S_OUT>,
0139 <&clk_core CLK_I2S>;
0140 clock-names = "sys", "ref";
0141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
0142 assigned-clock-rates = <12288000>;
0143 img,i2s-channels = <6>;
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&i2s_out_pins>;
0146 status = "disabled";
0147 resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
0148 reset-names = "rst";
0149 #sound-dai-cells = <0>;
0150 };
0151
0152 parallel_out: parallel-audio-out@18100c00 {
0153 compatible = "img,parallel-out";
0154 reg = <0x18100c00 0x100>;
0155 interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
0156 dmas = <&mdc 16 0xffffffff 0>;
0157 dma-names = "tx";
0158 clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
0159 <&clk_core CLK_AUDIO_DAC>;
0160 clock-names = "sys", "ref";
0161 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
0162 assigned-clock-rates = <12288000>;
0163 status = "disabled";
0164 resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
0165 reset-names = "rst";
0166 #sound-dai-cells = <0>;
0167 };
0168
0169 spdif_out: spdif-out@18100d00 {
0170 compatible = "img,spdif-out";
0171 reg = <0x18100d00 0x100>;
0172 interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
0173 dmas = <&mdc 14 0xffffffff 0>;
0174 dma-names = "tx";
0175 clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
0176 <&clk_core CLK_SPDIF>;
0177 clock-names = "sys", "ref";
0178 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
0179 assigned-clock-rates = <12288000>;
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&spdif_out_pin>;
0182 status = "disabled";
0183 resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
0184 reset-names = "rst";
0185 #sound-dai-cells = <0>;
0186 };
0187
0188 spdif_in: spdif-in@18100e00 {
0189 compatible = "img,spdif-in";
0190 reg = <0x18100e00 0x100>;
0191 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
0192 dmas = <&mdc 15 0xffffffff 0>;
0193 dma-names = "rx";
0194 clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
0195 clock-names = "sys";
0196 pinctrl-names = "default";
0197 pinctrl-0 = <&spdif_in_pin>;
0198 status = "disabled";
0199
0200 #sound-dai-cells = <0>;
0201 };
0202
0203 internal_dac: internal-dac {
0204 compatible = "img,pistachio-internal-dac";
0205 img,cr-top = <&cr_top>;
0206 img,voltage-select = <1>;
0207
0208 #sound-dai-cells = <0>;
0209 };
0210
0211 spfi0: spi@18100f00 {
0212 compatible = "img,spfi";
0213 reg = <0x18100f00 0x100>;
0214 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
0215 clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
0216 clock-names = "sys", "spfi";
0217 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
0218 dma-names = "rx", "tx";
0219 spfi-max-frequency = <50000000>;
0220 status = "disabled";
0221
0222 #address-cells = <1>;
0223 #size-cells = <0>;
0224 };
0225
0226 spfi1: spi@18101000 {
0227 compatible = "img,spfi";
0228 reg = <0x18101000 0x100>;
0229 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
0230 clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
0231 clock-names = "sys", "spfi";
0232 dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
0233 dma-names = "rx", "tx";
0234 img,supports-quad-mode;
0235 spfi-max-frequency = <50000000>;
0236 status = "disabled";
0237
0238 #address-cells = <1>;
0239 #size-cells = <0>;
0240 };
0241
0242 pwm: pwm@18101300 {
0243 compatible = "img,pistachio-pwm";
0244 reg = <0x18101300 0x100>;
0245 clocks = <&clk_periph PERIPH_CLK_PWM>,
0246 <&cr_periph SYS_CLK_PWM>;
0247 clock-names = "pwm", "sys";
0248 img,cr-periph = <&cr_periph>;
0249 #pwm-cells = <2>;
0250 status = "disabled";
0251 };
0252
0253 uart0: uart@18101400 {
0254 compatible = "snps,dw-apb-uart";
0255 reg = <0x18101400 0x100>;
0256 interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
0257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
0258 clock-names = "baudclk", "apb_pclk";
0259 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
0260 <&clk_core CLK_UART0_DIV>;
0261 reg-shift = <2>;
0262 reg-io-width = <4>;
0263 pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
0264 pinctrl-names = "default";
0265 status = "disabled";
0266 };
0267
0268 uart1: uart@18101500 {
0269 compatible = "snps,dw-apb-uart";
0270 reg = <0x18101500 0x100>;
0271 interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
0272 clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
0273 clock-names = "baudclk", "apb_pclk";
0274 assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
0275 <&clk_core CLK_UART1_DIV>;
0276 assigned-clock-rates = <114278400>, <1843200>;
0277 reg-shift = <2>;
0278 reg-io-width = <4>;
0279 pinctrl-0 = <&uart1_pins>;
0280 pinctrl-names = "default";
0281 status = "disabled";
0282 };
0283
0284 adc: adc@18101600 {
0285 compatible = "cosmic,10001-adc";
0286 reg = <0x18101600 0x24>;
0287 adc-reserved-channels = <0x30>;
0288 clocks = <&clk_core CLK_AUX_ADC>;
0289 clock-names = "adc";
0290 assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
0291 <&clk_core CLK_AUX_ADC_DIV>;
0292 assigned-clock-rates = <100000000>, <1000000>;
0293 status = "disabled";
0294
0295 #io-channel-cells = <1>;
0296 };
0297
0298 pinctrl: pinctrl@18101c00 {
0299 compatible = "img,pistachio-system-pinctrl";
0300 reg = <0x18101c00 0x400>;
0301
0302 gpio0: gpio0 {
0303 interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
0304
0305 gpio-controller;
0306 #gpio-cells = <2>;
0307 gpio-ranges = <&pinctrl 0 0 16>;
0308
0309 interrupt-controller;
0310 #interrupt-cells = <2>;
0311 };
0312
0313 gpio1: gpio1 {
0314 interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
0315
0316 gpio-controller;
0317 #gpio-cells = <2>;
0318 gpio-ranges = <&pinctrl 0 16 16>;
0319
0320 interrupt-controller;
0321 #interrupt-cells = <2>;
0322 };
0323
0324 gpio2: gpio2 {
0325 interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
0326
0327 gpio-controller;
0328 #gpio-cells = <2>;
0329 gpio-ranges = <&pinctrl 0 32 16>;
0330
0331 interrupt-controller;
0332 #interrupt-cells = <2>;
0333 };
0334
0335 gpio3: gpio3 {
0336 interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
0337
0338 gpio-controller;
0339 #gpio-cells = <2>;
0340 gpio-ranges = <&pinctrl 0 48 16>;
0341
0342 interrupt-controller;
0343 #interrupt-cells = <2>;
0344 };
0345
0346 gpio4: gpio4 {
0347 interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
0348
0349 gpio-controller;
0350 #gpio-cells = <2>;
0351 gpio-ranges = <&pinctrl 0 64 16>;
0352
0353 interrupt-controller;
0354 #interrupt-cells = <2>;
0355 };
0356
0357 gpio5: gpio5 {
0358 interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
0359
0360 gpio-controller;
0361 #gpio-cells = <2>;
0362 gpio-ranges = <&pinctrl 0 80 10>;
0363
0364 interrupt-controller;
0365 #interrupt-cells = <2>;
0366 };
0367
0368 i2c0_pins: i2c0-pins {
0369 pin_i2c0: i2c0 {
0370 pins = "mfio28", "mfio29";
0371 function = "i2c0";
0372 drive-strength = <4>;
0373 };
0374 };
0375
0376 i2c1_pins: i2c1-pins {
0377 pin_i2c1: i2c1 {
0378 pins = "mfio30", "mfio31";
0379 function = "i2c1";
0380 drive-strength = <4>;
0381 };
0382 };
0383
0384 i2c2_pins: i2c2-pins {
0385 pin_i2c2: i2c2 {
0386 pins = "mfio32", "mfio33";
0387 function = "i2c2";
0388 drive-strength = <4>;
0389 };
0390 };
0391
0392 i2c3_pins: i2c3-pins {
0393 pin_i2c3: i2c3 {
0394 pins = "mfio34", "mfio35";
0395 function = "i2c3";
0396 drive-strength = <4>;
0397 };
0398 };
0399
0400 spim0_pins: spim0-pins {
0401 pin_spim0: spim0 {
0402 pins = "mfio9", "mfio10";
0403 function = "spim0";
0404 drive-strength = <4>;
0405 };
0406 spim0_clk: spim0-clk {
0407 pins = "mfio8";
0408 function = "spim0";
0409 drive-strength = <4>;
0410 };
0411 };
0412
0413 spim0_cs0_alt_pin: spim0-cs0-alt-pin {
0414 spim0-cs0 {
0415 pins = "mfio2";
0416 drive-strength = <2>;
0417 };
0418 };
0419
0420 spim0_cs1_pin: spim0-cs1-pin {
0421 spim0-cs1 {
0422 pins = "mfio1";
0423 drive-strength = <2>;
0424 };
0425 };
0426
0427 spim0_cs2_pin: spim0-cs2-pin {
0428 spim0-cs2 {
0429 pins = "mfio55";
0430 drive-strength = <2>;
0431 };
0432 };
0433
0434 spim0_cs2_alt_pin: spim0-cs2-alt-pin {
0435 spim0-cs2 {
0436 pins = "mfio28";
0437 drive-strength = <2>;
0438 };
0439 };
0440
0441 spim0_cs3_pin: spim0-cs3-pin {
0442 spim0-cs3 {
0443 pins = "mfio56";
0444 drive-strength = <2>;
0445 };
0446 };
0447
0448 spim0_cs3_alt_pin: spim0-cs3-alt-pin {
0449 spim0-cs3 {
0450 pins = "mfio29";
0451 drive-strength = <2>;
0452 };
0453 };
0454
0455 spim0_cs4_pin: spim0-cs4-pin {
0456 spim0-cs4 {
0457 pins = "mfio57";
0458 drive-strength = <2>;
0459 };
0460 };
0461
0462 spim0_cs4_alt_pin: spim0-cs4-alt-pin {
0463 spim0-cs4 {
0464 pins = "mfio30";
0465 drive-strength = <2>;
0466 };
0467 };
0468
0469 spim1_pins: spim1-pins {
0470 spim1 {
0471 pins = "mfio3", "mfio4", "mfio5";
0472 function = "spim1";
0473 drive-strength = <2>;
0474 };
0475 };
0476
0477 spim1_quad_pins: spim1-quad-pins {
0478 spim1-quad {
0479 pins = "mfio6", "mfio7";
0480 function = "spim1";
0481 drive-strength = <2>;
0482 };
0483 };
0484
0485 spim1_cs0_pin: spim1-cs0-pins {
0486 spim1-cs0 {
0487 pins = "mfio0";
0488 function = "spim1";
0489 drive-strength = <2>;
0490 };
0491 };
0492
0493 spim1_cs1_pin: spim1-cs1-pin {
0494 spim1-cs1 {
0495 pins = "mfio1";
0496 function = "spim1";
0497 drive-strength = <2>;
0498 };
0499 };
0500
0501 spim1_cs1_alt_pin: spim1-cs1-alt-pin {
0502 spim1-cs1 {
0503 pins = "mfio58";
0504 function = "spim1";
0505 drive-strength = <2>;
0506 };
0507 };
0508
0509 spim1_cs2_pin: spim1-cs2-pin {
0510 spim1-cs2 {
0511 pins = "mfio2";
0512 function = "spim1";
0513 drive-strength = <2>;
0514 };
0515 };
0516
0517 spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
0518 spim1-cs2 {
0519 pins = "mfio31";
0520 function = "spim1";
0521 drive-strength = <2>;
0522 };
0523 };
0524
0525 spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
0526 spim1-cs2 {
0527 pins = "mfio55";
0528 function = "spim1";
0529 drive-strength = <2>;
0530 };
0531 };
0532
0533 spim1_cs3_pin: spim1-cs3-pin {
0534 spim1-cs3 {
0535 pins = "mfio56";
0536 function = "spim1";
0537 drive-strength = <2>;
0538 };
0539 };
0540
0541 spim1_cs4_pin: spim1-cs4-pin {
0542 spim1-cs4 {
0543 pins = "mfio57";
0544 function = "spim1";
0545 drive-strength = <2>;
0546 };
0547 };
0548
0549 uart0_pins: uart0-pins {
0550 uart0 {
0551 pins = "mfio55", "mfio56";
0552 function = "uart0";
0553 drive-strength = <2>;
0554 };
0555 };
0556
0557 uart0_rts_cts_pins: uart0-rts-cts-pins {
0558 uart0-rts-cts {
0559 pins = "mfio57", "mfio58";
0560 function = "uart0";
0561 drive-strength = <2>;
0562 };
0563 };
0564
0565 uart1_pins: uart1-pins {
0566 uart1 {
0567 pins = "mfio59", "mfio60";
0568 function = "uart1";
0569 drive-strength = <2>;
0570 };
0571 };
0572
0573 uart1_rts_cts_pins: uart1-rts-cts-pins {
0574 uart1-rts-cts {
0575 pins = "mfio1", "mfio2";
0576 function = "uart1";
0577 drive-strength = <2>;
0578 };
0579 };
0580
0581 enet_pins: enet-pins {
0582 pin_enet: enet {
0583 pins = "mfio63", "mfio64", "mfio65", "mfio66",
0584 "mfio67", "mfio68", "mfio69", "mfio70";
0585 function = "eth";
0586 slew-rate = <1>;
0587 drive-strength = <4>;
0588 };
0589 pin_enet_phy_clk: enet-phy-clk {
0590 pins = "mfio71";
0591 function = "eth";
0592 slew-rate = <1>;
0593 drive-strength = <8>;
0594 };
0595 };
0596
0597 sdhost_pins: sdhost-pins {
0598 pin_sdhost_clk: sdhost-clk {
0599 pins = "mfio15";
0600 function = "sdhost";
0601 slew-rate = <1>;
0602 drive-strength = <4>;
0603 };
0604 pin_sdhost_cmd: sdhost-cmd {
0605 pins = "mfio16";
0606 function = "sdhost";
0607 slew-rate = <1>;
0608 drive-strength = <4>;
0609 };
0610 pin_sdhost_data: sdhost-data {
0611 pins = "mfio17", "mfio18", "mfio19", "mfio20",
0612 "mfio21", "mfio22", "mfio23", "mfio24";
0613 function = "sdhost";
0614 slew-rate = <1>;
0615 drive-strength = <4>;
0616 };
0617 pin_sdhost_power_select: sdhost-power-select {
0618 pins = "mfio25";
0619 function = "sdhost";
0620 slew-rate = <1>;
0621 drive-strength = <2>;
0622 };
0623 pin_sdhost_card_detect: sdhost-card-detect {
0624 pins = "mfio26";
0625 function = "sdhost";
0626 drive-strength = <2>;
0627 };
0628 pin_sdhost_write_protect: sdhost-write-protect {
0629 pins = "mfio27";
0630 function = "sdhost";
0631 drive-strength = <2>;
0632 };
0633 };
0634
0635 ir_pin: ir-pin {
0636 ir-data {
0637 pins = "mfio72";
0638 function = "ir";
0639 drive-strength = <2>;
0640 };
0641 };
0642
0643 pwmpdm0_pin: pwmpdm0-pin {
0644 pwmpdm0 {
0645 pins = "mfio73";
0646 function = "pwmpdm";
0647 drive-strength = <2>;
0648 };
0649 };
0650
0651 pwmpdm1_pin: pwmpdm1-pin {
0652 pwmpdm1 {
0653 pins = "mfio74";
0654 function = "pwmpdm";
0655 drive-strength = <2>;
0656 };
0657 };
0658
0659 pwmpdm2_pin: pwmpdm2-pin {
0660 pwmpdm2 {
0661 pins = "mfio75";
0662 function = "pwmpdm";
0663 drive-strength = <2>;
0664 };
0665 };
0666
0667 pwmpdm3_pin: pwmpdm3-pin {
0668 pwmpdm3 {
0669 pins = "mfio76";
0670 function = "pwmpdm";
0671 drive-strength = <2>;
0672 };
0673 };
0674
0675 dac_clk_pin: dac-clk-pin {
0676 pin_dac_clk: dac-clk {
0677 pins = "mfio45";
0678 function = "i2s_dac_clk";
0679 drive-strength = <4>;
0680 };
0681 };
0682
0683 i2s_mclk_pin: i2s-mclk-pin {
0684 pin_i2s_mclk: i2s-mclk {
0685 pins = "mfio36";
0686 function = "i2s_out";
0687 drive-strength = <4>;
0688 };
0689 };
0690
0691 spdif_out_pin: spdif-out-pin {
0692 spdif-out {
0693 pins = "mfio61";
0694 function = "spdif_out";
0695 slew-rate = <1>;
0696 drive-strength = <2>;
0697 };
0698 };
0699
0700 spdif_in_pin: spdif-in-pin {
0701 spdif-in {
0702 pins = "mfio62";
0703 function = "spdif_in";
0704 drive-strength = <2>;
0705 };
0706 };
0707
0708 i2s_out_pins: i2s-out-pins {
0709 pins_i2s_out_clk: i2s-out-clk {
0710 pins = "mfio37", "mfio38";
0711 function = "i2s_out";
0712 drive-strength = <4>;
0713 };
0714 pins_i2s_out: i2s-out {
0715 pins = "mfio39", "mfio40",
0716 "mfio41", "mfio42",
0717 "mfio43", "mfio44";
0718 function = "i2s_out";
0719 drive-strength = <2>;
0720 };
0721 };
0722
0723 i2s_in_pins: i2s-in-pins {
0724 i2s-in {
0725 pins = "mfio47", "mfio48", "mfio49",
0726 "mfio50", "mfio51", "mfio52",
0727 "mfio53", "mfio54";
0728 function = "i2s_in";
0729 drive-strength = <2>;
0730 };
0731 };
0732 };
0733
0734 timer: timer@18102000 {
0735 compatible = "img,pistachio-gptimer";
0736 reg = <0x18102000 0x100>;
0737 interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
0738 clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
0739 <&cr_periph SYS_CLK_TIMER>;
0740 clock-names = "fast", "sys";
0741 img,cr-periph = <&cr_periph>;
0742 };
0743
0744 wdt: watchdog@18102100 {
0745 compatible = "img,pdc-wdt";
0746 reg = <0x18102100 0x100>;
0747 interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
0748 clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
0749 clock-names = "wdt", "sys";
0750 assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
0751 <&clk_periph PERIPH_CLK_WD_DIV>;
0752 assigned-clock-rates = <4000000>, <32768>;
0753 };
0754
0755 ir: ir@18102200 {
0756 compatible = "img,ir-rev1";
0757 reg = <0x18102200 0x100>;
0758 interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
0759 clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
0760 clock-names = "core", "sys";
0761 assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
0762 <&clk_periph PERIPH_CLK_IR_DIV>;
0763 assigned-clock-rates = <4000000>, <32768>;
0764 pinctrl-0 = <&ir_pin>;
0765 pinctrl-names = "default";
0766 status = "disabled";
0767 };
0768
0769 usb: usb@18120000 {
0770 compatible = "snps,dwc2";
0771 reg = <0x18120000 0x1c000>;
0772 interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
0773 phys = <&usb_phy>;
0774 phy-names = "usb2-phy";
0775 g-tx-fifo-size = <256 256 256 256>;
0776 status = "disabled";
0777 };
0778
0779 enet: ethernet@18140000 {
0780 compatible = "snps,dwmac";
0781 reg = <0x18140000 0x2000>;
0782 interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
0783 interrupt-names = "macirq";
0784 clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
0785 clock-names = "stmmaceth", "pclk";
0786 assigned-clocks = <&clk_core CLK_ENET_MUX>,
0787 <&clk_core CLK_ENET_DIV>;
0788 assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
0789 assigned-clock-rates = <0>, <50000000>;
0790 pinctrl-0 = <&enet_pins>;
0791 pinctrl-names = "default";
0792 phy-mode = "rmii";
0793 status = "disabled";
0794 };
0795
0796 sdhost: mmc@18142000 {
0797 compatible = "img,pistachio-dw-mshc";
0798 reg = <0x18142000 0x400>;
0799 interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
0800 clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
0801 clock-names = "ciu", "biu";
0802 pinctrl-0 = <&sdhost_pins>;
0803 pinctrl-names = "default";
0804 fifo-depth = <0x20>;
0805 clock-frequency = <50000000>;
0806 bus-width = <8>;
0807 cap-mmc-highspeed;
0808 cap-sd-highspeed;
0809 status = "disabled";
0810 };
0811
0812 sram: sram@1b000000 {
0813 compatible = "mmio-sram";
0814 reg = <0x1b000000 0x10000>;
0815 };
0816
0817 mdc: dma-controller@18143000 {
0818 compatible = "img,pistachio-mdc-dma";
0819 reg = <0x18143000 0x1000>;
0820 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
0821 <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
0822 <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
0823 <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
0824 <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
0825 <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
0826 <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
0827 <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
0828 <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
0829 <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
0830 <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
0831 <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
0832 clocks = <&cr_periph SYS_CLK_MDC>;
0833 clock-names = "sys";
0834
0835 img,max-burst-multiplier = <16>;
0836 img,cr-periph = <&cr_periph>;
0837
0838 #dma-cells = <3>;
0839 };
0840
0841 clk_core: clk@18144000 {
0842 compatible = "img,pistachio-clk", "syscon";
0843 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
0844 <&cr_top EXT_CLK_ENET_IN>;
0845 clock-names = "xtal", "audio_refclk_ext_gate",
0846 "ext_enet_in_gate";
0847 reg = <0x18144000 0x800>;
0848 #clock-cells = <1>;
0849 };
0850
0851 clk_periph: clk@18144800 {
0852 compatible = "img,pistachio-clk-periph";
0853 reg = <0x18144800 0x1000>;
0854 clocks = <&clk_core CLK_PERIPH_SYS>;
0855 clock-names = "periph_sys_core";
0856 #clock-cells = <1>;
0857 };
0858
0859 cr_periph: clk@18148000 {
0860 compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
0861 reg = <0x18148000 0x1000>;
0862 clocks = <&clk_periph PERIPH_CLK_SYS>;
0863 clock-names = "sys";
0864 #clock-cells = <1>;
0865
0866 pistachio_reset: reset-controller {
0867 compatible = "img,pistachio-reset";
0868 #reset-cells = <1>;
0869 };
0870 };
0871
0872 cr_top: clk@18149000 {
0873 compatible = "img,pistachio-cr-top", "syscon";
0874 reg = <0x18149000 0x200>;
0875 #clock-cells = <1>;
0876 };
0877
0878 hash: hash@18149600 {
0879 compatible = "img,hash-accelerator";
0880 reg = <0x18149600 0x100>, <0x18101100 0x4>;
0881 interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
0882 dmas = <&mdc 8 0xffffffff 0>;
0883 dma-names = "tx";
0884 clocks = <&cr_periph SYS_CLK_HASH>,
0885 <&clk_periph PERIPH_CLK_ROM>;
0886 clock-names = "sys", "hash";
0887 };
0888
0889 gic: interrupt-controller@1bdc0000 {
0890 compatible = "mti,gic";
0891 reg = <0x1bdc0000 0x20000>;
0892
0893 interrupt-controller;
0894 #interrupt-cells = <3>;
0895
0896 timer {
0897 compatible = "mti,gic-timer";
0898 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
0899 clocks = <&clk_core CLK_MIPS>;
0900 };
0901 };
0902
0903 cpc: cpc@1bde0000 {
0904 compatible = "mti,mips-cpc";
0905 reg = <0x1bde0000 0x10000>;
0906 };
0907
0908 cdmm: cdmm@1bdf0000 {
0909 compatible = "mti,mips-cdmm";
0910 reg = <0x1bdf0000 0x10000>;
0911 };
0912
0913 usb_phy: usb-phy {
0914 compatible = "img,pistachio-usb-phy";
0915 clocks = <&clk_core CLK_USB_PHY>;
0916 clock-names = "usb_phy";
0917 assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
0918 assigned-clock-rates = <50000000>;
0919 img,refclk = <0x2>;
0920 img,cr-top = <&cr_top>;
0921 #phy-cells = <0>;
0922 };
0923
0924 xtal: xtal {
0925 compatible = "fixed-clock";
0926 #clock-cells = <0>;
0927 clock-frequency = <52000000>;
0928 clock-output-names = "xtal";
0929 };
0930 };
