0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/clock/boston-clock.h>
0005 #include <dt-bindings/gpio/gpio.h>
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/mips-gic.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 compatible = "img,boston";
0013
0014 chosen {
0015 stdout-path = "uart0:115200";
0016 };
0017
0018 aliases {
0019 uart0 = &uart0;
0020 };
0021
0022 cpus {
0023 #address-cells = <1>;
0024 #size-cells = <0>;
0025
0026 cpu@0 {
0027 device_type = "cpu";
0028 compatible = "img,mips";
0029 reg = <0>;
0030 clocks = <&clk_boston BOSTON_CLK_CPU>;
0031 };
0032 };
0033
0034 memory@0 {
0035 device_type = "memory";
0036 reg = <0x00000000 0x10000000>;
0037 };
0038
0039 pci0: pci@10000000 {
0040 compatible = "xlnx,axi-pcie-host-1.00.a";
0041 device_type = "pci";
0042 reg = <0x10000000 0x2000000>;
0043
0044 #address-cells = <3>;
0045 #size-cells = <2>;
0046 #interrupt-cells = <1>;
0047
0048 interrupt-parent = <&gic>;
0049 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
0050
0051 ranges = <0x02000000 0 0x40000000
0052 0x40000000 0 0x40000000>;
0053
0054 bus-range = <0x00 0xff>;
0055
0056 interrupt-map-mask = <0 0 0 7>;
0057 interrupt-map = <0 0 0 1 &pci0_intc 1>,
0058 <0 0 0 2 &pci0_intc 2>,
0059 <0 0 0 3 &pci0_intc 3>,
0060 <0 0 0 4 &pci0_intc 4>;
0061
0062 pci0_intc: interrupt-controller {
0063 interrupt-controller;
0064 #address-cells = <0>;
0065 #interrupt-cells = <1>;
0066 };
0067 };
0068
0069 pci1: pci@12000000 {
0070 compatible = "xlnx,axi-pcie-host-1.00.a";
0071 device_type = "pci";
0072 reg = <0x12000000 0x2000000>;
0073
0074 #address-cells = <3>;
0075 #size-cells = <2>;
0076 #interrupt-cells = <1>;
0077
0078 interrupt-parent = <&gic>;
0079 interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
0080
0081 ranges = <0x02000000 0 0x20000000
0082 0x20000000 0 0x20000000>;
0083
0084 bus-range = <0x00 0xff>;
0085
0086 interrupt-map-mask = <0 0 0 7>;
0087 interrupt-map = <0 0 0 1 &pci1_intc 1>,
0088 <0 0 0 2 &pci1_intc 2>,
0089 <0 0 0 3 &pci1_intc 3>,
0090 <0 0 0 4 &pci1_intc 4>;
0091
0092 pci1_intc: interrupt-controller {
0093 interrupt-controller;
0094 #address-cells = <0>;
0095 #interrupt-cells = <1>;
0096 };
0097 };
0098
0099 pci2: pci@14000000 {
0100 compatible = "xlnx,axi-pcie-host-1.00.a";
0101 device_type = "pci";
0102 reg = <0x14000000 0x2000000>;
0103
0104 #address-cells = <3>;
0105 #size-cells = <2>;
0106 #interrupt-cells = <1>;
0107
0108 interrupt-parent = <&gic>;
0109 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
0110
0111 ranges = <0x02000000 0 0x16000000
0112 0x16000000 0 0x100000>;
0113
0114 bus-range = <0x00 0xff>;
0115
0116 interrupt-map-mask = <0 0 0 7>;
0117 interrupt-map = <0 0 0 1 &pci2_intc 1>,
0118 <0 0 0 2 &pci2_intc 2>,
0119 <0 0 0 3 &pci2_intc 3>,
0120 <0 0 0 4 &pci2_intc 4>;
0121
0122 pci2_intc: interrupt-controller {
0123 interrupt-controller;
0124 #address-cells = <0>;
0125 #interrupt-cells = <1>;
0126 };
0127
0128 pci2_root@0,0,0 {
0129 compatible = "pci10ee,7021";
0130 reg = <0x00000000 0 0 0 0>;
0131
0132 #address-cells = <3>;
0133 #size-cells = <2>;
0134 #interrupt-cells = <1>;
0135
0136 eg20t_bridge@1,0,0 {
0137 compatible = "pci8086,8800";
0138 reg = <0x00010000 0 0 0 0>;
0139
0140 #address-cells = <3>;
0141 #size-cells = <2>;
0142 #interrupt-cells = <1>;
0143
0144 eg20t_phub@2,0,0 {
0145 compatible = "pci8086,8801";
0146 reg = <0x00020000 0 0 0 0>;
0147 intel,eg20t-prefetch = <0>;
0148 };
0149
0150 eg20t_mac@2,0,1 {
0151 compatible = "pci8086,8802";
0152 reg = <0x00020100 0 0 0 0>;
0153 phy-reset-gpios = <&eg20t_gpio 6
0154 GPIO_ACTIVE_LOW>;
0155 };
0156
0157 eg20t_gpio: eg20t_gpio@2,0,2 {
0158 compatible = "pci8086,8803";
0159 reg = <0x00020200 0 0 0 0>;
0160
0161 gpio-controller;
0162 #gpio-cells = <2>;
0163 };
0164
0165 eg20t_i2c@2,12,2 {
0166 compatible = "pci8086,8817";
0167 reg = <0x00026200 0 0 0 0>;
0168
0169 #address-cells = <1>;
0170 #size-cells = <0>;
0171
0172 rtc@68 {
0173 compatible = "st,m41t81s";
0174 reg = <0x68>;
0175 };
0176 };
0177 };
0178 };
0179 };
0180
0181 gic: interrupt-controller@16120000 {
0182 compatible = "mti,gic";
0183 reg = <0x16120000 0x20000>;
0184
0185 interrupt-controller;
0186 #interrupt-cells = <3>;
0187
0188 timer {
0189 compatible = "mti,gic-timer";
0190 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
0191 clocks = <&clk_boston BOSTON_CLK_CPU>;
0192 };
0193 };
0194
0195 cdmm@16140000 {
0196 compatible = "mti,mips-cdmm";
0197 reg = <0x16140000 0x8000>;
0198 };
0199
0200 cpc@16200000 {
0201 compatible = "mti,mips-cpc";
0202 reg = <0x16200000 0x8000>;
0203 };
0204
0205 plat_regs: system-controller@17ffd000 {
0206 compatible = "img,boston-platform-regs", "syscon";
0207 reg = <0x17ffd000 0x1000>;
0208
0209 clk_boston: clock {
0210 compatible = "img,boston-clock";
0211 #clock-cells = <1>;
0212 };
0213 };
0214
0215 reboot: syscon-reboot {
0216 compatible = "syscon-reboot";
0217 regmap = <&plat_regs>;
0218 offset = <0x10>;
0219 mask = <0x10>;
0220 };
0221
0222 uart0: uart@17ffe000 {
0223 compatible = "ns16550a";
0224 reg = <0x17ffe000 0x1000>;
0225 reg-shift = <2>;
0226
0227 interrupt-parent = <&gic>;
0228 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
0229
0230 clocks = <&clk_boston BOSTON_CLK_SYS>;
0231 };
0232
0233 lcd: lcd@17fff000 {
0234 compatible = "img,boston-lcd";
0235 reg = <0x17fff000 0x8>;
0236 };
0237 };
