OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003 /*
0004 * OCTEON 68XX device tree skeleton.
0005 *
0006 * This device tree is pruned and patched by early boot code before
0007 * use. Because of this, it contains a super-set of the available
0008 * devices and properties.
0009 */
0010 / {
0011 compatible = "cavium,octeon-6880";
0012 #address-cells = <2>;
0013 #size-cells = <2>;
0014 interrupt-parent = <&ciu2>;
0015
0016 soc@0 {
0017 compatible = "simple-bus";
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020 ranges; /* Direct mapping */
0021
0022 ciu2: interrupt-controller@1070100000000 {
0023 compatible = "cavium,octeon-6880-ciu2";
0024 interrupt-controller;
0025 /* Interrupts are specified by two parts:
0026 * 1) Controller register (0 or 7)
0027 * 2) Bit within the register (0..63)
0028 */
0029 #address-cells = <0>;
0030 #interrupt-cells = <2>;
0031 reg = <0x10701 0x00000000 0x0 0x4000000>;
0032 };
0033
0034 gpio: gpio-controller@1070000000800 {
0035 #gpio-cells = <2>;
0036 compatible = "cavium,octeon-3860-gpio";
0037 reg = <0x10700 0x00000800 0x0 0x100>;
0038 gpio-controller;
0039 /* Interrupts are specified by two parts:
0040 * 1) GPIO pin number (0..15)
0041 * 2) Triggering (1 - edge rising
0042 * 2 - edge falling
0043 * 4 - level active high
0044 * 8 - level active low)
0045 */
0046 interrupt-controller;
0047 #interrupt-cells = <2>;
0048 /* The GPIO pins connect to 16 consecutive CUI bits */
0049 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
0050 <7 4>, <7 5>, <7 6>, <7 7>,
0051 <7 8>, <7 9>, <7 10>, <7 11>,
0052 <7 12>, <7 13>, <7 14>, <7 15>;
0053 };
0054
0055 smi0: mdio@1180000003800 {
0056 compatible = "cavium,octeon-3860-mdio";
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059 reg = <0x11800 0x00003800 0x0 0x40>;
0060
0061 phy0: ethernet-phy@6 {
0062 compatible = "marvell,88e1118";
0063 marvell,reg-init =
0064 /* Fix rx and tx clock transition timing */
0065 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
0066 /* Adjust LED drive. */
0067 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
0068 /* irq, blink-activity, blink-link */
0069 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
0070 reg = <6>;
0071 };
0072
0073 phy1: ethernet-phy@1 {
0074 cavium,qlm-trim = "4,sgmii";
0075 reg = <1>;
0076 compatible = "marvell,88e1149r";
0077 marvell,reg-init = <3 0x10 0 0x5777>,
0078 <3 0x11 0 0x00aa>,
0079 <3 0x12 0 0x4105>,
0080 <3 0x13 0 0x0a60>;
0081 };
0082 phy2: ethernet-phy@2 {
0083 cavium,qlm-trim = "4,sgmii";
0084 reg = <2>;
0085 compatible = "marvell,88e1149r";
0086 marvell,reg-init = <3 0x10 0 0x5777>,
0087 <3 0x11 0 0x00aa>,
0088 <3 0x12 0 0x4105>,
0089 <3 0x13 0 0x0a60>;
0090 };
0091 phy3: ethernet-phy@3 {
0092 cavium,qlm-trim = "4,sgmii";
0093 reg = <3>;
0094 compatible = "marvell,88e1149r";
0095 marvell,reg-init = <3 0x10 0 0x5777>,
0096 <3 0x11 0 0x00aa>,
0097 <3 0x12 0 0x4105>,
0098 <3 0x13 0 0x0a60>;
0099 };
0100 phy4: ethernet-phy@4 {
0101 cavium,qlm-trim = "4,sgmii";
0102 reg = <4>;
0103 compatible = "marvell,88e1149r";
0104 marvell,reg-init = <3 0x10 0 0x5777>,
0105 <3 0x11 0 0x00aa>,
0106 <3 0x12 0 0x4105>,
0107 <3 0x13 0 0x0a60>;
0108 };
0109 };
0110
0111 smi1: mdio@1180000003880 {
0112 compatible = "cavium,octeon-3860-mdio";
0113 #address-cells = <1>;
0114 #size-cells = <0>;
0115 reg = <0x11800 0x00003880 0x0 0x40>;
0116
0117 phy41: ethernet-phy@1 {
0118 cavium,qlm-trim = "0,sgmii";
0119 reg = <1>;
0120 compatible = "marvell,88e1149r";
0121 marvell,reg-init = <3 0x10 0 0x5777>,
0122 <3 0x11 0 0x00aa>,
0123 <3 0x12 0 0x4105>,
0124 <3 0x13 0 0x0a60>;
0125 };
0126 phy42: ethernet-phy@2 {
0127 cavium,qlm-trim = "0,sgmii";
0128 reg = <2>;
0129 compatible = "marvell,88e1149r";
0130 marvell,reg-init = <3 0x10 0 0x5777>,
0131 <3 0x11 0 0x00aa>,
0132 <3 0x12 0 0x4105>,
0133 <3 0x13 0 0x0a60>;
0134 };
0135 phy43: ethernet-phy@3 {
0136 cavium,qlm-trim = "0,sgmii";
0137 reg = <3>;
0138 compatible = "marvell,88e1149r";
0139 marvell,reg-init = <3 0x10 0 0x5777>,
0140 <3 0x11 0 0x00aa>,
0141 <3 0x12 0 0x4105>,
0142 <3 0x13 0 0x0a60>;
0143 };
0144 phy44: ethernet-phy@4 {
0145 cavium,qlm-trim = "0,sgmii";
0146 reg = <4>;
0147 compatible = "marvell,88e1149r";
0148 marvell,reg-init = <3 0x10 0 0x5777>,
0149 <3 0x11 0 0x00aa>,
0150 <3 0x12 0 0x4105>,
0151 <3 0x13 0 0x0a60>;
0152 };
0153 };
0154
0155 smi2: mdio@1180000003900 {
0156 compatible = "cavium,octeon-3860-mdio";
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159 reg = <0x11800 0x00003900 0x0 0x40>;
0160
0161 phy21: ethernet-phy@1 {
0162 cavium,qlm-trim = "2,sgmii";
0163 reg = <1>;
0164 compatible = "marvell,88e1149r";
0165 marvell,reg-init = <3 0x10 0 0x5777>,
0166 <3 0x11 0 0x00aa>,
0167 <3 0x12 0 0x4105>,
0168 <3 0x13 0 0x0a60>;
0169 };
0170 phy22: ethernet-phy@2 {
0171 cavium,qlm-trim = "2,sgmii";
0172 reg = <2>;
0173 compatible = "marvell,88e1149r";
0174 marvell,reg-init = <3 0x10 0 0x5777>,
0175 <3 0x11 0 0x00aa>,
0176 <3 0x12 0 0x4105>,
0177 <3 0x13 0 0x0a60>;
0178 };
0179 phy23: ethernet-phy@3 {
0180 cavium,qlm-trim = "2,sgmii";
0181 reg = <3>;
0182 compatible = "marvell,88e1149r";
0183 marvell,reg-init = <3 0x10 0 0x5777>,
0184 <3 0x11 0 0x00aa>,
0185 <3 0x12 0 0x4105>,
0186 <3 0x13 0 0x0a60>;
0187 };
0188 phy24: ethernet-phy@4 {
0189 cavium,qlm-trim = "2,sgmii";
0190 reg = <4>;
0191 compatible = "marvell,88e1149r";
0192 marvell,reg-init = <3 0x10 0 0x5777>,
0193 <3 0x11 0 0x00aa>,
0194 <3 0x12 0 0x4105>,
0195 <3 0x13 0 0x0a60>;
0196 };
0197 };
0198
0199 smi3: mdio@1180000003980 {
0200 compatible = "cavium,octeon-3860-mdio";
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 reg = <0x11800 0x00003980 0x0 0x40>;
0204
0205 phy11: ethernet-phy@1 {
0206 cavium,qlm-trim = "3,sgmii";
0207 reg = <1>;
0208 compatible = "marvell,88e1149r";
0209 marvell,reg-init = <3 0x10 0 0x5777>,
0210 <3 0x11 0 0x00aa>,
0211 <3 0x12 0 0x4105>,
0212 <3 0x13 0 0x0a60>;
0213 };
0214 phy12: ethernet-phy@2 {
0215 cavium,qlm-trim = "3,sgmii";
0216 reg = <2>;
0217 compatible = "marvell,88e1149r";
0218 marvell,reg-init = <3 0x10 0 0x5777>,
0219 <3 0x11 0 0x00aa>,
0220 <3 0x12 0 0x4105>,
0221 <3 0x13 0 0x0a60>;
0222 };
0223 phy13: ethernet-phy@3 {
0224 cavium,qlm-trim = "3,sgmii";
0225 reg = <3>;
0226 compatible = "marvell,88e1149r";
0227 marvell,reg-init = <3 0x10 0 0x5777>,
0228 <3 0x11 0 0x00aa>,
0229 <3 0x12 0 0x4105>,
0230 <3 0x13 0 0x0a60>;
0231 };
0232 phy14: ethernet-phy@4 {
0233 cavium,qlm-trim = "3,sgmii";
0234 reg = <4>;
0235 compatible = "marvell,88e1149r";
0236 marvell,reg-init = <3 0x10 0 0x5777>,
0237 <3 0x11 0 0x00aa>,
0238 <3 0x12 0 0x4105>,
0239 <3 0x13 0 0x0a60>;
0240 };
0241 };
0242
0243 mix0: ethernet@1070000100000 {
0244 compatible = "cavium,octeon-5750-mix";
0245 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
0246 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
0247 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
0248 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
0249 cell-index = <0>;
0250 interrupts = <6 40>, <6 32>;
0251 local-mac-address = [ 00 00 00 00 00 00 ];
0252 phy-handle = <&phy0>;
0253 };
0254
0255 pip: pip@11800a0000000 {
0256 compatible = "cavium,octeon-3860-pip";
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259 reg = <0x11800 0xa0000000 0x0 0x2000>;
0260
0261 interface@4 {
0262 compatible = "cavium,octeon-3860-pip-interface";
0263 #address-cells = <1>;
0264 #size-cells = <0>;
0265 reg = <0x4>; /* interface */
0266
0267 ethernet@0 {
0268 compatible = "cavium,octeon-3860-pip-port";
0269 reg = <0x0>; /* Port */
0270 local-mac-address = [ 00 00 00 00 00 00 ];
0271 phy-handle = <&phy1>;
0272 };
0273 ethernet@1 {
0274 compatible = "cavium,octeon-3860-pip-port";
0275 reg = <0x1>; /* Port */
0276 local-mac-address = [ 00 00 00 00 00 00 ];
0277 phy-handle = <&phy2>;
0278 };
0279 ethernet@2 {
0280 compatible = "cavium,octeon-3860-pip-port";
0281 reg = <0x2>; /* Port */
0282 local-mac-address = [ 00 00 00 00 00 00 ];
0283 phy-handle = <&phy3>;
0284 };
0285 ethernet@3 {
0286 compatible = "cavium,octeon-3860-pip-port";
0287 reg = <0x3>; /* Port */
0288 local-mac-address = [ 00 00 00 00 00 00 ];
0289 phy-handle = <&phy4>;
0290 };
0291 };
0292
0293 interface@3 {
0294 compatible = "cavium,octeon-3860-pip-interface";
0295 #address-cells = <1>;
0296 #size-cells = <0>;
0297 reg = <0x3>; /* interface */
0298
0299 ethernet@0 {
0300 compatible = "cavium,octeon-3860-pip-port";
0301 reg = <0x0>; /* Port */
0302 local-mac-address = [ 00 00 00 00 00 00 ];
0303 phy-handle = <&phy11>;
0304 };
0305 ethernet@1 {
0306 compatible = "cavium,octeon-3860-pip-port";
0307 reg = <0x1>; /* Port */
0308 local-mac-address = [ 00 00 00 00 00 00 ];
0309 phy-handle = <&phy12>;
0310 };
0311 ethernet@2 {
0312 compatible = "cavium,octeon-3860-pip-port";
0313 reg = <0x2>; /* Port */
0314 local-mac-address = [ 00 00 00 00 00 00 ];
0315 phy-handle = <&phy13>;
0316 };
0317 ethernet@3 {
0318 compatible = "cavium,octeon-3860-pip-port";
0319 reg = <0x3>; /* Port */
0320 local-mac-address = [ 00 00 00 00 00 00 ];
0321 phy-handle = <&phy14>;
0322 };
0323 };
0324
0325 interface@2 {
0326 compatible = "cavium,octeon-3860-pip-interface";
0327 #address-cells = <1>;
0328 #size-cells = <0>;
0329 reg = <0x2>; /* interface */
0330
0331 ethernet@0 {
0332 compatible = "cavium,octeon-3860-pip-port";
0333 reg = <0x0>; /* Port */
0334 local-mac-address = [ 00 00 00 00 00 00 ];
0335 phy-handle = <&phy21>;
0336 };
0337 ethernet@1 {
0338 compatible = "cavium,octeon-3860-pip-port";
0339 reg = <0x1>; /* Port */
0340 local-mac-address = [ 00 00 00 00 00 00 ];
0341 phy-handle = <&phy22>;
0342 };
0343 ethernet@2 {
0344 compatible = "cavium,octeon-3860-pip-port";
0345 reg = <0x2>; /* Port */
0346 local-mac-address = [ 00 00 00 00 00 00 ];
0347 phy-handle = <&phy23>;
0348 };
0349 ethernet@3 {
0350 compatible = "cavium,octeon-3860-pip-port";
0351 reg = <0x3>; /* Port */
0352 local-mac-address = [ 00 00 00 00 00 00 ];
0353 phy-handle = <&phy24>;
0354 };
0355 };
0356
0357 interface@1 {
0358 compatible = "cavium,octeon-3860-pip-interface";
0359 #address-cells = <1>;
0360 #size-cells = <0>;
0361 reg = <0x1>; /* interface */
0362
0363 ethernet@0 {
0364 compatible = "cavium,octeon-3860-pip-port";
0365 reg = <0x0>; /* Port */
0366 local-mac-address = [ 00 00 00 00 00 00 ];
0367 };
0368 };
0369
0370 interface@0 {
0371 compatible = "cavium,octeon-3860-pip-interface";
0372 #address-cells = <1>;
0373 #size-cells = <0>;
0374 reg = <0x0>; /* interface */
0375
0376 ethernet@0 {
0377 compatible = "cavium,octeon-3860-pip-port";
0378 reg = <0x0>; /* Port */
0379 local-mac-address = [ 00 00 00 00 00 00 ];
0380 phy-handle = <&phy41>;
0381 };
0382 ethernet@1 {
0383 compatible = "cavium,octeon-3860-pip-port";
0384 reg = <0x1>; /* Port */
0385 local-mac-address = [ 00 00 00 00 00 00 ];
0386 phy-handle = <&phy42>;
0387 };
0388 ethernet@2 {
0389 compatible = "cavium,octeon-3860-pip-port";
0390 reg = <0x2>; /* Port */
0391 local-mac-address = [ 00 00 00 00 00 00 ];
0392 phy-handle = <&phy43>;
0393 };
0394 ethernet@3 {
0395 compatible = "cavium,octeon-3860-pip-port";
0396 reg = <0x3>; /* Port */
0397 local-mac-address = [ 00 00 00 00 00 00 ];
0398 phy-handle = <&phy44>;
0399 };
0400 };
0401 };
0402
0403 twsi0: i2c@1180000001000 {
0404 #address-cells = <1>;
0405 #size-cells = <0>;
0406 compatible = "cavium,octeon-3860-twsi";
0407 reg = <0x11800 0x00001000 0x0 0x200>;
0408 interrupts = <3 32>;
0409 clock-frequency = <100000>;
0410
0411 rtc@68 {
0412 compatible = "dallas,ds1337";
0413 reg = <0x68>;
0414 };
0415 tmp@4c {
0416 compatible = "ti,tmp421";
0417 reg = <0x4c>;
0418 };
0419 };
0420
0421 twsi1: i2c@1180000001200 {
0422 #address-cells = <1>;
0423 #size-cells = <0>;
0424 compatible = "cavium,octeon-3860-twsi";
0425 reg = <0x11800 0x00001200 0x0 0x200>;
0426 interrupts = <3 33>;
0427 clock-frequency = <100000>;
0428 };
0429
0430 uart0: serial@1180000000800 {
0431 compatible = "cavium,octeon-3860-uart","ns16550";
0432 reg = <0x11800 0x00000800 0x0 0x400>;
0433 clock-frequency = <0>;
0434 current-speed = <115200>;
0435 reg-shift = <3>;
0436 interrupts = <3 36>;
0437 };
0438
0439 uart1: serial@1180000000c00 {
0440 compatible = "cavium,octeon-3860-uart","ns16550";
0441 reg = <0x11800 0x00000c00 0x0 0x400>;
0442 clock-frequency = <0>;
0443 current-speed = <115200>;
0444 reg-shift = <3>;
0445 interrupts = <3 37>;
0446 };
0447
0448 bootbus: bootbus@1180000000000 {
0449 compatible = "cavium,octeon-3860-bootbus";
0450 reg = <0x11800 0x00000000 0x0 0x200>;
0451 /* The chip select number and offset */
0452 #address-cells = <2>;
0453 /* The size of the chip select region */
0454 #size-cells = <1>;
0455 ranges = <0 0 0 0x1f400000 0xc00000>,
0456 <1 0 0x10000 0x30000000 0>,
0457 <2 0 0x10000 0x40000000 0>,
0458 <3 0 0x10000 0x50000000 0>,
0459 <4 0 0 0x1d020000 0x10000>,
0460 <5 0 0 0x1d040000 0x10000>,
0461 <6 0 0 0x1d050000 0x10000>,
0462 <7 0 0x10000 0x90000000 0>;
0463
0464 cavium,cs-config@0 {
0465 compatible = "cavium,octeon-3860-bootbus-config";
0466 cavium,cs-index = <0>;
0467 cavium,t-adr = <10>;
0468 cavium,t-ce = <50>;
0469 cavium,t-oe = <50>;
0470 cavium,t-we = <35>;
0471 cavium,t-rd-hld = <25>;
0472 cavium,t-wr-hld = <35>;
0473 cavium,t-pause = <0>;
0474 cavium,t-wait = <300>;
0475 cavium,t-page = <25>;
0476 cavium,t-rd-dly = <0>;
0477
0478 cavium,pages = <0>;
0479 cavium,bus-width = <8>;
0480 };
0481 cavium,cs-config@4 {
0482 compatible = "cavium,octeon-3860-bootbus-config";
0483 cavium,cs-index = <4>;
0484 cavium,t-adr = <320>;
0485 cavium,t-ce = <320>;
0486 cavium,t-oe = <320>;
0487 cavium,t-we = <320>;
0488 cavium,t-rd-hld = <320>;
0489 cavium,t-wr-hld = <320>;
0490 cavium,t-pause = <320>;
0491 cavium,t-wait = <320>;
0492 cavium,t-page = <320>;
0493 cavium,t-rd-dly = <0>;
0494
0495 cavium,pages = <0>;
0496 cavium,bus-width = <8>;
0497 };
0498 cavium,cs-config@5 {
0499 compatible = "cavium,octeon-3860-bootbus-config";
0500 cavium,cs-index = <5>;
0501 cavium,t-adr = <0>;
0502 cavium,t-ce = <300>;
0503 cavium,t-oe = <125>;
0504 cavium,t-we = <150>;
0505 cavium,t-rd-hld = <100>;
0506 cavium,t-wr-hld = <300>;
0507 cavium,t-pause = <0>;
0508 cavium,t-wait = <300>;
0509 cavium,t-page = <310>;
0510 cavium,t-rd-dly = <0>;
0511
0512 cavium,pages = <0>;
0513 cavium,bus-width = <16>;
0514 };
0515 cavium,cs-config@6 {
0516 compatible = "cavium,octeon-3860-bootbus-config";
0517 cavium,cs-index = <6>;
0518 cavium,t-adr = <0>;
0519 cavium,t-ce = <30>;
0520 cavium,t-oe = <125>;
0521 cavium,t-we = <150>;
0522 cavium,t-rd-hld = <100>;
0523 cavium,t-wr-hld = <30>;
0524 cavium,t-pause = <0>;
0525 cavium,t-wait = <30>;
0526 cavium,t-page = <310>;
0527 cavium,t-rd-dly = <0>;
0528
0529 cavium,pages = <0>;
0530 cavium,wait-mode;
0531 cavium,bus-width = <16>;
0532 };
0533
0534 flash0: nor@0,0 {
0535 compatible = "cfi-flash";
0536 reg = <0 0 0x800000>;
0537 #address-cells = <1>;
0538 #size-cells = <1>;
0539
0540 partition@0 {
0541 label = "bootloader";
0542 reg = <0 0x200000>;
0543 read-only;
0544 };
0545 partition@200000 {
0546 label = "kernel";
0547 reg = <0x200000 0x200000>;
0548 };
0549 partition@400000 {
0550 label = "cramfs";
0551 reg = <0x400000 0x3fe000>;
0552 };
0553 partition@7fe000 {
0554 label = "environment";
0555 reg = <0x7fe000 0x2000>;
0556 read-only;
0557 };
0558 };
0559
0560 led0: led-display@4,0 {
0561 compatible = "avago,hdsp-253x";
0562 reg = <4 0x20 0x20>, <4 0 0x20>;
0563 };
0564
0565 compact-flash@5,0 {
0566 compatible = "cavium,ebt3000-compact-flash";
0567 reg = <5 0 0x10000>, <6 0 0x10000>;
0568 cavium,bus-width = <16>;
0569 cavium,true-ide;
0570 cavium,dma-engine-handle = <&dma0>;
0571 };
0572 };
0573
0574 dma0: dma-engine@1180000000100 {
0575 compatible = "cavium,octeon-5750-bootbus-dma";
0576 reg = <0x11800 0x00000100 0x0 0x8>;
0577 interrupts = <0 63>;
0578 };
0579 dma1: dma-engine@1180000000108 {
0580 compatible = "cavium,octeon-5750-bootbus-dma";
0581 reg = <0x11800 0x00000108 0x0 0x8>;
0582 interrupts = <0 63>;
0583 };
0584
0585 uctl: uctl@118006f000000 {
0586 compatible = "cavium,octeon-6335-uctl";
0587 reg = <0x11800 0x6f000000 0x0 0x100>;
0588 ranges; /* Direct mapping */
0589 #address-cells = <2>;
0590 #size-cells = <2>;
0591 /* 12MHz, 24MHz and 48MHz allowed */
0592 refclk-frequency = <12000000>;
0593 /* Either "crystal" or "external" */
0594 refclk-type = "crystal";
0595
0596 ehci@16f0000000000 {
0597 compatible = "cavium,octeon-6335-ehci","usb-ehci";
0598 reg = <0x16f00 0x00000000 0x0 0x100>;
0599 interrupts = <3 44>;
0600 big-endian-regs;
0601 };
0602 ohci@16f0000000400 {
0603 compatible = "cavium,octeon-6335-ohci","usb-ohci";
0604 reg = <0x16f00 0x00000400 0x0 0x100>;
0605 interrupts = <3 44>;
0606 big-endian-regs;
0607 };
0608 };
0609 };
0610
0611 aliases {
0612 mix0 = &mix0;
0613 pip = &pip;
0614 smi0 = &smi0;
0615 smi1 = &smi1;
0616 smi2 = &smi2;
0617 smi3 = &smi3;
0618 twsi0 = &twsi0;
0619 twsi1 = &twsi1;
0620 uart0 = &uart0;
0621 uart1 = &uart1;
0622 uctl = &uctl;
0623 led0 = &led0;
0624 flash0 = &flash0;
0625 };
0626 };
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