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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
0004 *
0005 * This device tree is pruned and patched by early boot code before
0006 * use. Because of this, it contains a super-set of the available
0007 * devices and properties.
0008 */
0009
0010 /include/ "octeon_3xxx.dtsi"
0011
0012 / {
0013 soc@0 {
0014 smi0: mdio@1180000001800 {
0015 phy0: ethernet-phy@0 {
0016 compatible = "marvell,88e1118";
0017 marvell,reg-init =
0018 /* Fix rx and tx clock transition timing */
0019 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
0020 /* Adjust LED drive. */
0021 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
0022 /* irq, blink-activity, blink-link */
0023 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
0024 reg = <0>;
0025 };
0026
0027 phy1: ethernet-phy@1 {
0028 compatible = "marvell,88e1118";
0029 marvell,reg-init =
0030 /* Fix rx and tx clock transition timing */
0031 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
0032 /* Adjust LED drive. */
0033 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
0034 /* irq, blink-activity, blink-link */
0035 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
0036 reg = <1>;
0037 };
0038
0039 phy2: ethernet-phy@2 {
0040 reg = <2>;
0041 compatible = "marvell,88e1149r";
0042 marvell,reg-init = <3 0x10 0 0x5777>,
0043 <3 0x11 0 0x00aa>,
0044 <3 0x12 0 0x4105>,
0045 <3 0x13 0 0x0a60>;
0046 };
0047 phy3: ethernet-phy@3 {
0048 reg = <3>;
0049 compatible = "marvell,88e1149r";
0050 marvell,reg-init = <3 0x10 0 0x5777>,
0051 <3 0x11 0 0x00aa>,
0052 <3 0x12 0 0x4105>,
0053 <3 0x13 0 0x0a60>;
0054 };
0055 phy4: ethernet-phy@4 {
0056 reg = <4>;
0057 compatible = "marvell,88e1149r";
0058 marvell,reg-init = <3 0x10 0 0x5777>,
0059 <3 0x11 0 0x00aa>,
0060 <3 0x12 0 0x4105>,
0061 <3 0x13 0 0x0a60>;
0062 };
0063 phy5: ethernet-phy@5 {
0064 reg = <5>;
0065 compatible = "marvell,88e1149r";
0066 marvell,reg-init = <3 0x10 0 0x5777>,
0067 <3 0x11 0 0x00aa>,
0068 <3 0x12 0 0x4105>,
0069 <3 0x13 0 0x0a60>;
0070 };
0071
0072 phy6: ethernet-phy@6 {
0073 reg = <6>;
0074 compatible = "marvell,88e1149r";
0075 marvell,reg-init = <3 0x10 0 0x5777>,
0076 <3 0x11 0 0x00aa>,
0077 <3 0x12 0 0x4105>,
0078 <3 0x13 0 0x0a60>;
0079 };
0080 phy7: ethernet-phy@7 {
0081 reg = <7>;
0082 compatible = "marvell,88e1149r";
0083 marvell,reg-init = <3 0x10 0 0x5777>,
0084 <3 0x11 0 0x00aa>,
0085 <3 0x12 0 0x4105>,
0086 <3 0x13 0 0x0a60>;
0087 };
0088 phy8: ethernet-phy@8 {
0089 reg = <8>;
0090 compatible = "marvell,88e1149r";
0091 marvell,reg-init = <3 0x10 0 0x5777>,
0092 <3 0x11 0 0x00aa>,
0093 <3 0x12 0 0x4105>,
0094 <3 0x13 0 0x0a60>;
0095 };
0096 phy9: ethernet-phy@9 {
0097 reg = <9>;
0098 compatible = "marvell,88e1149r";
0099 marvell,reg-init = <3 0x10 0 0x5777>,
0100 <3 0x11 0 0x00aa>,
0101 <3 0x12 0 0x4105>,
0102 <3 0x13 0 0x0a60>;
0103 };
0104 };
0105
0106 smi1: mdio@1180000001900 {
0107 compatible = "cavium,octeon-3860-mdio";
0108 #address-cells = <1>;
0109 #size-cells = <0>;
0110 reg = <0x11800 0x00001900 0x0 0x40>;
0111
0112 phy100: ethernet-phy@1 {
0113 reg = <1>;
0114 compatible = "marvell,88e1149r";
0115 marvell,reg-init = <3 0x10 0 0x5777>,
0116 <3 0x11 0 0x00aa>,
0117 <3 0x12 0 0x4105>,
0118 <3 0x13 0 0x0a60>;
0119 interrupt-parent = <&gpio>;
0120 interrupts = <12 8>; /* Pin 12, active low */
0121 };
0122 phy101: ethernet-phy@2 {
0123 reg = <2>;
0124 compatible = "marvell,88e1149r";
0125 marvell,reg-init = <3 0x10 0 0x5777>,
0126 <3 0x11 0 0x00aa>,
0127 <3 0x12 0 0x4105>,
0128 <3 0x13 0 0x0a60>;
0129 interrupt-parent = <&gpio>;
0130 interrupts = <12 8>; /* Pin 12, active low */
0131 };
0132 phy102: ethernet-phy@3 {
0133 reg = <3>;
0134 compatible = "marvell,88e1149r";
0135 marvell,reg-init = <3 0x10 0 0x5777>,
0136 <3 0x11 0 0x00aa>,
0137 <3 0x12 0 0x4105>,
0138 <3 0x13 0 0x0a60>;
0139 interrupt-parent = <&gpio>;
0140 interrupts = <12 8>; /* Pin 12, active low */
0141 };
0142 phy103: ethernet-phy@4 {
0143 reg = <4>;
0144 compatible = "marvell,88e1149r";
0145 marvell,reg-init = <3 0x10 0 0x5777>,
0146 <3 0x11 0 0x00aa>,
0147 <3 0x12 0 0x4105>,
0148 <3 0x13 0 0x0a60>;
0149 interrupt-parent = <&gpio>;
0150 interrupts = <12 8>; /* Pin 12, active low */
0151 };
0152 };
0153
0154 mix0: ethernet@1070000100000 {
0155 compatible = "cavium,octeon-5750-mix";
0156 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
0157 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
0158 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
0159 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
0160 cell-index = <0>;
0161 interrupts = <0 62>, <1 46>;
0162 local-mac-address = [ 00 00 00 00 00 00 ];
0163 phy-handle = <&phy0>;
0164 };
0165
0166 mix1: ethernet@1070000100800 {
0167 compatible = "cavium,octeon-5750-mix";
0168 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
0169 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
0170 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
0171 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
0172 cell-index = <1>;
0173 interrupts = <1 18>, < 1 46>;
0174 local-mac-address = [ 00 00 00 00 00 00 ];
0175 phy-handle = <&phy1>;
0176 };
0177
0178 pip: pip@11800a0000000 {
0179 interface@0 {
0180 ethernet@0 {
0181 phy-handle = <&phy2>;
0182 cavium,alt-phy-handle = <&phy100>;
0183 rx-delay = <0>;
0184 tx-delay = <0>;
0185 fixed-link {
0186 speed = <1000>;
0187 full-duplex;
0188 };
0189 };
0190 ethernet@1 {
0191 phy-handle = <&phy3>;
0192 cavium,alt-phy-handle = <&phy101>;
0193 rx-delay = <0>;
0194 tx-delay = <0>;
0195 fixed-link {
0196 speed = <1000>;
0197 full-duplex;
0198 };
0199 };
0200 ethernet@2 {
0201 phy-handle = <&phy4>;
0202 cavium,alt-phy-handle = <&phy102>;
0203 rx-delay = <0>;
0204 tx-delay = <0>;
0205 };
0206 ethernet@3 {
0207 compatible = "cavium,octeon-3860-pip-port";
0208 reg = <0x3>; /* Port */
0209 local-mac-address = [ 00 00 00 00 00 00 ];
0210 phy-handle = <&phy5>;
0211 cavium,alt-phy-handle = <&phy103>;
0212 };
0213 ethernet@4 {
0214 compatible = "cavium,octeon-3860-pip-port";
0215 reg = <0x4>; /* Port */
0216 local-mac-address = [ 00 00 00 00 00 00 ];
0217 };
0218 ethernet@5 {
0219 compatible = "cavium,octeon-3860-pip-port";
0220 reg = <0x5>; /* Port */
0221 local-mac-address = [ 00 00 00 00 00 00 ];
0222 };
0223 ethernet@6 {
0224 compatible = "cavium,octeon-3860-pip-port";
0225 reg = <0x6>; /* Port */
0226 local-mac-address = [ 00 00 00 00 00 00 ];
0227 };
0228 ethernet@7 {
0229 compatible = "cavium,octeon-3860-pip-port";
0230 reg = <0x7>; /* Port */
0231 local-mac-address = [ 00 00 00 00 00 00 ];
0232 };
0233 ethernet@8 {
0234 compatible = "cavium,octeon-3860-pip-port";
0235 reg = <0x8>; /* Port */
0236 local-mac-address = [ 00 00 00 00 00 00 ];
0237 };
0238 ethernet@9 {
0239 compatible = "cavium,octeon-3860-pip-port";
0240 reg = <0x9>; /* Port */
0241 local-mac-address = [ 00 00 00 00 00 00 ];
0242 };
0243 ethernet@a {
0244 compatible = "cavium,octeon-3860-pip-port";
0245 reg = <0xa>; /* Port */
0246 local-mac-address = [ 00 00 00 00 00 00 ];
0247 };
0248 ethernet@b {
0249 compatible = "cavium,octeon-3860-pip-port";
0250 reg = <0xb>; /* Port */
0251 local-mac-address = [ 00 00 00 00 00 00 ];
0252 };
0253 ethernet@c {
0254 compatible = "cavium,octeon-3860-pip-port";
0255 reg = <0xc>; /* Port */
0256 local-mac-address = [ 00 00 00 00 00 00 ];
0257 };
0258 ethernet@d {
0259 compatible = "cavium,octeon-3860-pip-port";
0260 reg = <0xd>; /* Port */
0261 local-mac-address = [ 00 00 00 00 00 00 ];
0262 };
0263 ethernet@e {
0264 compatible = "cavium,octeon-3860-pip-port";
0265 reg = <0xe>; /* Port */
0266 local-mac-address = [ 00 00 00 00 00 00 ];
0267 };
0268 ethernet@f {
0269 compatible = "cavium,octeon-3860-pip-port";
0270 reg = <0xf>; /* Port */
0271 local-mac-address = [ 00 00 00 00 00 00 ];
0272 };
0273 };
0274
0275 interface@1 {
0276 ethernet@0 {
0277 compatible = "cavium,octeon-3860-pip-port";
0278 reg = <0x0>; /* Port */
0279 local-mac-address = [ 00 00 00 00 00 00 ];
0280 phy-handle = <&phy6>;
0281 };
0282 ethernet@1 {
0283 compatible = "cavium,octeon-3860-pip-port";
0284 reg = <0x1>; /* Port */
0285 local-mac-address = [ 00 00 00 00 00 00 ];
0286 phy-handle = <&phy7>;
0287 };
0288 ethernet@2 {
0289 compatible = "cavium,octeon-3860-pip-port";
0290 reg = <0x2>; /* Port */
0291 local-mac-address = [ 00 00 00 00 00 00 ];
0292 phy-handle = <&phy8>;
0293 };
0294 ethernet@3 {
0295 compatible = "cavium,octeon-3860-pip-port";
0296 reg = <0x3>; /* Port */
0297 local-mac-address = [ 00 00 00 00 00 00 ];
0298 phy-handle = <&phy9>;
0299 };
0300 };
0301 };
0302
0303 twsi0: i2c@1180000001000 {
0304 rtc@68 {
0305 compatible = "dallas,ds1337";
0306 reg = <0x68>;
0307 };
0308 tmp@4c {
0309 compatible = "ti,tmp421";
0310 reg = <0x4c>;
0311 };
0312 };
0313
0314 twsi1: i2c@1180000001200 {
0315 #address-cells = <1>;
0316 #size-cells = <0>;
0317 compatible = "cavium,octeon-3860-twsi";
0318 reg = <0x11800 0x00001200 0x0 0x200>;
0319 interrupts = <0 59>;
0320 clock-frequency = <100000>;
0321 };
0322
0323 uart1: serial@1180000000c00 {
0324 compatible = "cavium,octeon-3860-uart","ns16550";
0325 reg = <0x11800 0x00000c00 0x0 0x400>;
0326 clock-frequency = <0>;
0327 current-speed = <115200>;
0328 reg-shift = <3>;
0329 interrupts = <0 35>;
0330 };
0331
0332 uart2: serial@1180000000400 {
0333 compatible = "cavium,octeon-3860-uart","ns16550";
0334 reg = <0x11800 0x00000400 0x0 0x400>;
0335 clock-frequency = <0>;
0336 current-speed = <115200>;
0337 reg-shift = <3>;
0338 interrupts = <1 16>;
0339 };
0340
0341 bootbus: bootbus@1180000000000 {
0342 led0: led-display@4,0 {
0343 compatible = "avago,hdsp-253x";
0344 reg = <4 0x20 0x20>, <4 0 0x20>;
0345 };
0346
0347 cf0: compact-flash@5,0 {
0348 compatible = "cavium,ebt3000-compact-flash";
0349 reg = <5 0 0x10000>, <6 0 0x10000>;
0350 cavium,bus-width = <16>;
0351 cavium,true-ide;
0352 cavium,dma-engine-handle = <&dma0>;
0353 };
0354 };
0355
0356 uctl: uctl@118006f000000 {
0357 compatible = "cavium,octeon-6335-uctl";
0358 reg = <0x11800 0x6f000000 0x0 0x100>;
0359 ranges; /* Direct mapping */
0360 #address-cells = <2>;
0361 #size-cells = <2>;
0362 /* 12MHz, 24MHz and 48MHz allowed */
0363 refclk-frequency = <12000000>;
0364 /* Either "crystal" or "external" */
0365 refclk-type = "crystal";
0366
0367 ehci@16f0000000000 {
0368 compatible = "cavium,octeon-6335-ehci","usb-ehci";
0369 reg = <0x16f00 0x00000000 0x0 0x100>;
0370 interrupts = <0 56>;
0371 big-endian-regs;
0372 };
0373 ohci@16f0000000400 {
0374 compatible = "cavium,octeon-6335-ohci","usb-ohci";
0375 reg = <0x16f00 0x00000400 0x0 0x100>;
0376 interrupts = <0 56>;
0377 big-endian-regs;
0378 };
0379 };
0380
0381 usbn: usbn@1180068000000 {
0382 /* 12MHz, 24MHz and 48MHz allowed */
0383 refclk-frequency = <12000000>;
0384 /* Either "crystal" or "external" */
0385 refclk-type = "crystal";
0386 };
0387 };
0388
0389 aliases {
0390 mix0 = &mix0;
0391 mix1 = &mix1;
0392 pip = &pip;
0393 smi0 = &smi0;
0394 smi1 = &smi1;
0395 twsi0 = &twsi0;
0396 twsi1 = &twsi1;
0397 uart0 = &uart0;
0398 uart1 = &uart1;
0399 uart2 = &uart2;
0400 flash0 = &flash0;
0401 cf0 = &cf0;
0402 uctl = &uctl;
0403 usbn = &usbn;
0404 led0 = &led0;
0405 };
0406 };
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