0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7425";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <163125000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips5000";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018
0019 cpu@1 {
0020 compatible = "brcm,bmips5000";
0021 device_type = "cpu";
0022 reg = <1>;
0023 };
0024 };
0025
0026 aliases {
0027 uart0 = &uart0;
0028 };
0029
0030 cpu_intc: interrupt-controller {
0031 #address-cells = <0>;
0032 compatible = "mti,cpu-interrupt-controller";
0033
0034 interrupt-controller;
0035 #interrupt-cells = <1>;
0036 };
0037
0038 clocks {
0039 uart_clk: uart_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <81000000>;
0043 };
0044
0045 upg_clk: upg_clk {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <27000000>;
0049 };
0050 };
0051
0052 rdb {
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 compatible = "simple-bus";
0057 ranges = <0 0x10000000 0x01000000>;
0058
0059 periph_intc: interrupt-controller@41a400 {
0060 compatible = "brcm,bcm7038-l1-intc";
0061 reg = <0x41a400 0x30>, <0x41a600 0x30>;
0062
0063 interrupt-controller;
0064 #interrupt-cells = <1>;
0065
0066 interrupt-parent = <&cpu_intc>;
0067 interrupts = <2>, <3>;
0068 };
0069
0070 sun_l2_intc: interrupt-controller@403000 {
0071 compatible = "brcm,l2-intc";
0072 reg = <0x403000 0x30>;
0073 interrupt-controller;
0074 #interrupt-cells = <1>;
0075 interrupt-parent = <&periph_intc>;
0076 interrupts = <47>;
0077 };
0078
0079 gisb-arb@400000 {
0080 compatible = "brcm,bcm7400-gisb-arb";
0081 reg = <0x400000 0xdc>;
0082 native-endian;
0083 interrupt-parent = <&sun_l2_intc>;
0084 interrupts = <0>, <2>;
0085 brcm,gisb-arb-master-mask = <0x177b>;
0086 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
0087 "bsp_0", "rdc_0",
0088 "raaga_0", "avd_1",
0089 "jtag_0", "svd_0",
0090 "vice_0";
0091 };
0092
0093 upg_irq0_intc: interrupt-controller@406780 {
0094 compatible = "brcm,bcm7120-l2-intc";
0095 reg = <0x406780 0x8>;
0096
0097 brcm,int-map-mask = <0x44>, <0x7000000>;
0098 brcm,int-fwd-mask = <0x70000>;
0099
0100 interrupt-controller;
0101 #interrupt-cells = <1>;
0102
0103 interrupt-parent = <&periph_intc>;
0104 interrupts = <55>, <53>;
0105 interrupt-names = "upg_main", "upg_bsc";
0106 };
0107
0108 upg_aon_irq0_intc: interrupt-controller@409480 {
0109 compatible = "brcm,bcm7120-l2-intc";
0110 reg = <0x409480 0x8>;
0111
0112 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
0113 brcm,int-fwd-mask = <0>;
0114 brcm,irq-can-wake;
0115
0116 interrupt-controller;
0117 #interrupt-cells = <1>;
0118
0119 interrupt-parent = <&periph_intc>;
0120 interrupts = <56>, <54>, <59>;
0121 interrupt-names = "upg_main_aon", "upg_bsc_aon",
0122 "upg_spi";
0123 };
0124
0125 sun_top_ctrl: syscon@404000 {
0126 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
0127 reg = <0x404000 0x51c>;
0128 native-endian;
0129 };
0130
0131 reboot {
0132 compatible = "brcm,brcmstb-reboot";
0133 syscon = <&sun_top_ctrl 0x304 0x308>;
0134 };
0135
0136 uart0: serial@406b00 {
0137 compatible = "ns16550a";
0138 reg = <0x406b00 0x20>;
0139 reg-io-width = <0x4>;
0140 reg-shift = <0x2>;
0141 interrupt-parent = <&periph_intc>;
0142 interrupts = <61>;
0143 clocks = <&uart_clk>;
0144 status = "disabled";
0145 };
0146
0147 uart1: serial@406b40 {
0148 compatible = "ns16550a";
0149 reg = <0x406b40 0x20>;
0150 reg-io-width = <0x4>;
0151 reg-shift = <0x2>;
0152 interrupt-parent = <&periph_intc>;
0153 interrupts = <62>;
0154 clocks = <&uart_clk>;
0155 status = "disabled";
0156 };
0157
0158 uart2: serial@406b80 {
0159 compatible = "ns16550a";
0160 reg = <0x406b80 0x20>;
0161 reg-io-width = <0x4>;
0162 reg-shift = <0x2>;
0163 interrupt-parent = <&periph_intc>;
0164 interrupts = <63>;
0165 clocks = <&uart_clk>;
0166 status = "disabled";
0167 };
0168
0169 bsca: i2c@409180 {
0170 clock-frequency = <390000>;
0171 compatible = "brcm,brcmstb-i2c";
0172 interrupt-parent = <&upg_aon_irq0_intc>;
0173 reg = <0x409180 0x58>;
0174 interrupts = <27>;
0175 interrupt-names = "upg_bsca";
0176 status = "disabled";
0177 };
0178
0179 bscb: i2c@409400 {
0180 clock-frequency = <390000>;
0181 compatible = "brcm,brcmstb-i2c";
0182 interrupt-parent = <&upg_aon_irq0_intc>;
0183 reg = <0x409400 0x58>;
0184 interrupts = <28>;
0185 interrupt-names = "upg_bscb";
0186 status = "disabled";
0187 };
0188
0189 bscc: i2c@406200 {
0190 clock-frequency = <390000>;
0191 compatible = "brcm,brcmstb-i2c";
0192 interrupt-parent = <&upg_irq0_intc>;
0193 reg = <0x406200 0x58>;
0194 interrupts = <24>;
0195 interrupt-names = "upg_bscc";
0196 status = "disabled";
0197 };
0198
0199 bscd: i2c@406280 {
0200 clock-frequency = <390000>;
0201 compatible = "brcm,brcmstb-i2c";
0202 interrupt-parent = <&upg_irq0_intc>;
0203 reg = <0x406280 0x58>;
0204 interrupts = <25>;
0205 interrupt-names = "upg_bscd";
0206 status = "disabled";
0207 };
0208
0209 bsce: i2c@406300 {
0210 clock-frequency = <390000>;
0211 compatible = "brcm,brcmstb-i2c";
0212 interrupt-parent = <&upg_irq0_intc>;
0213 reg = <0x406300 0x58>;
0214 interrupts = <26>;
0215 interrupt-names = "upg_bsce";
0216 status = "disabled";
0217 };
0218
0219 pwma: pwm@406580 {
0220 compatible = "brcm,bcm7038-pwm";
0221 reg = <0x406580 0x28>;
0222 #pwm-cells = <2>;
0223 clocks = <&upg_clk>;
0224 status = "disabled";
0225 };
0226
0227 pwmb: pwm@406800 {
0228 compatible = "brcm,bcm7038-pwm";
0229 reg = <0x406800 0x28>;
0230 #pwm-cells = <2>;
0231 clocks = <&upg_clk>;
0232 status = "disabled";
0233 };
0234
0235 watchdog: watchdog@4067e8 {
0236 clocks = <&upg_clk>;
0237 compatible = "brcm,bcm7038-wdt";
0238 reg = <0x4067e8 0x14>;
0239 status = "disabled";
0240 };
0241
0242 aon_pm_l2_intc: interrupt-controller@408440 {
0243 compatible = "brcm,l2-intc";
0244 reg = <0x408440 0x30>;
0245 interrupt-controller;
0246 #interrupt-cells = <1>;
0247 interrupt-parent = <&periph_intc>;
0248 interrupts = <49>;
0249 brcm,irq-can-wake;
0250 };
0251
0252 aon_ctrl: syscon@408000 {
0253 compatible = "brcm,brcmstb-aon-ctrl";
0254 reg = <0x408000 0x100>, <0x408200 0x200>;
0255 reg-names = "aon-ctrl", "aon-sram";
0256 };
0257
0258 timers: timer@4067c0 {
0259 compatible = "brcm,brcmstb-timers";
0260 reg = <0x4067c0 0x40>;
0261 };
0262
0263 upg_gio: gpio@406700 {
0264 compatible = "brcm,brcmstb-gpio";
0265 reg = <0x406700 0x80>;
0266 #gpio-cells = <2>;
0267 #interrupt-cells = <2>;
0268 gpio-controller;
0269 interrupt-controller;
0270 interrupt-parent = <&upg_irq0_intc>;
0271 interrupts = <6>;
0272 brcm,gpio-bank-widths = <32 32 32 21>;
0273 };
0274
0275 upg_gio_aon: gpio@4094c0 {
0276 compatible = "brcm,brcmstb-gpio";
0277 reg = <0x4094c0 0x40>;
0278 #gpio-cells = <2>;
0279 #interrupt-cells = <2>;
0280 gpio-controller;
0281 interrupt-controller;
0282 interrupt-parent = <&upg_aon_irq0_intc>;
0283 interrupts = <6>;
0284 interrupts-extended = <&upg_aon_irq0_intc 6>,
0285 <&aon_pm_l2_intc 5>;
0286 wakeup-source;
0287 brcm,gpio-bank-widths = <18 4>;
0288 };
0289
0290 enet0: ethernet@b80000 {
0291 phy-mode = "internal";
0292 phy-handle = <&phy1>;
0293 mac-address = [ 00 10 18 36 23 1a ];
0294 compatible = "brcm,genet-v3";
0295 #address-cells = <0x1>;
0296 #size-cells = <0x1>;
0297 reg = <0xb80000 0x11c88>;
0298 interrupts = <17>, <18>;
0299 interrupt-parent = <&periph_intc>;
0300 status = "disabled";
0301
0302 mdio@e14 {
0303 compatible = "brcm,genet-mdio-v3";
0304 #address-cells = <0x1>;
0305 #size-cells = <0x0>;
0306 reg = <0xe14 0x8>;
0307
0308 phy1: ethernet-phy@1 {
0309 max-speed = <100>;
0310 reg = <0x1>;
0311 compatible = "brcm,40nm-ephy",
0312 "ethernet-phy-ieee802.3-c22";
0313 };
0314 };
0315 };
0316
0317 ehci0: usb@480300 {
0318 compatible = "brcm,bcm7425-ehci", "generic-ehci";
0319 reg = <0x480300 0x100>;
0320 native-endian;
0321 interrupt-parent = <&periph_intc>;
0322 interrupts = <65>;
0323 status = "disabled";
0324 };
0325
0326 ohci0: usb@480400 {
0327 compatible = "brcm,bcm7425-ohci", "generic-ohci";
0328 reg = <0x480400 0x100>;
0329 native-endian;
0330 no-big-frame-no;
0331 interrupt-parent = <&periph_intc>;
0332 interrupts = <67>;
0333 status = "disabled";
0334 };
0335
0336 ehci1: usb@480500 {
0337 compatible = "brcm,bcm7425-ehci", "generic-ehci";
0338 reg = <0x480500 0x100>;
0339 native-endian;
0340 interrupt-parent = <&periph_intc>;
0341 interrupts = <66>;
0342 status = "disabled";
0343 };
0344
0345 ohci1: usb@480600 {
0346 compatible = "brcm,bcm7425-ohci", "generic-ohci";
0347 reg = <0x480600 0x100>;
0348 native-endian;
0349 no-big-frame-no;
0350 interrupt-parent = <&periph_intc>;
0351 interrupts = <68>;
0352 status = "disabled";
0353 };
0354
0355 ehci2: usb@490300 {
0356 compatible = "brcm,bcm7425-ehci", "generic-ehci";
0357 reg = <0x490300 0x100>;
0358 native-endian;
0359 interrupt-parent = <&periph_intc>;
0360 interrupts = <70>;
0361 status = "disabled";
0362 };
0363
0364 ohci2: usb@490400 {
0365 compatible = "brcm,bcm7425-ohci", "generic-ohci";
0366 reg = <0x490400 0x100>;
0367 native-endian;
0368 no-big-frame-no;
0369 interrupt-parent = <&periph_intc>;
0370 interrupts = <72>;
0371 status = "disabled";
0372 };
0373
0374 ehci3: usb@490500 {
0375 compatible = "brcm,bcm7425-ehci", "generic-ehci";
0376 reg = <0x490500 0x100>;
0377 native-endian;
0378 interrupt-parent = <&periph_intc>;
0379 interrupts = <71>;
0380 status = "disabled";
0381 };
0382
0383 ohci3: usb@490600 {
0384 compatible = "brcm,bcm7425-ohci", "generic-ohci";
0385 reg = <0x490600 0x100>;
0386 native-endian;
0387 no-big-frame-no;
0388 interrupt-parent = <&periph_intc>;
0389 interrupts = <73>;
0390 status = "disabled";
0391 };
0392
0393 hif_l2_intc: interrupt-controller@41a000 {
0394 compatible = "brcm,l2-intc";
0395 reg = <0x41a000 0x30>;
0396 interrupt-controller;
0397 #interrupt-cells = <1>;
0398 interrupt-parent = <&periph_intc>;
0399 interrupts = <24>;
0400 };
0401
0402 nand: nand@41b800 {
0403 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
0404 #address-cells = <1>;
0405 #size-cells = <0>;
0406 reg-names = "nand", "flash-edu";
0407 reg = <0x41b800 0x400>, <0x41bc00 0x24>;
0408 interrupt-parent = <&hif_l2_intc>;
0409 interrupts = <24>;
0410 status = "disabled";
0411 };
0412
0413 sata: sata@181000 {
0414 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
0415 reg-names = "ahci", "top-ctrl";
0416 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
0417 interrupt-parent = <&periph_intc>;
0418 interrupts = <41>;
0419 #address-cells = <1>;
0420 #size-cells = <0>;
0421 status = "disabled";
0422
0423 sata0: sata-port@0 {
0424 reg = <0>;
0425 phys = <&sata_phy0>;
0426 };
0427
0428 sata1: sata-port@1 {
0429 reg = <1>;
0430 phys = <&sata_phy1>;
0431 };
0432 };
0433
0434 sata_phy: sata-phy@180100 {
0435 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
0436 reg = <0x180100 0x0eff>;
0437 reg-names = "phy";
0438 #address-cells = <1>;
0439 #size-cells = <0>;
0440 status = "disabled";
0441
0442 sata_phy0: sata-phy@0 {
0443 reg = <0>;
0444 #phy-cells = <0>;
0445 };
0446
0447 sata_phy1: sata-phy@1 {
0448 reg = <1>;
0449 #phy-cells = <0>;
0450 };
0451 };
0452
0453 sdhci0: sdhci@419000 {
0454 compatible = "brcm,bcm7425-sdhci";
0455 reg = <0x419000 0x100>;
0456 interrupt-parent = <&periph_intc>;
0457 interrupts = <43>;
0458 sd-uhs-sdr50;
0459 mmc-hs200-1_8v;
0460 status = "disabled";
0461 };
0462
0463 sdhci1: sdhci@419200 {
0464 compatible = "brcm,bcm7425-sdhci";
0465 reg = <0x419200 0x100>;
0466 interrupt-parent = <&periph_intc>;
0467 interrupts = <44>;
0468 sd-uhs-sdr50;
0469 mmc-hs200-1_8v;
0470 status = "disabled";
0471 };
0472
0473 spi_l2_intc: interrupt-controller@41ad00 {
0474 compatible = "brcm,l2-intc";
0475 reg = <0x41ad00 0x30>;
0476 interrupt-controller;
0477 #interrupt-cells = <1>;
0478 interrupt-parent = <&periph_intc>;
0479 interrupts = <25>;
0480 };
0481
0482 qspi: spi@41c000 {
0483 #address-cells = <0x1>;
0484 #size-cells = <0x0>;
0485 compatible = "brcm,spi-bcm-qspi",
0486 "brcm,spi-brcmstb-qspi";
0487 clocks = <&upg_clk>;
0488 reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
0489 reg-names = "cs_reg", "hif_mspi", "bspi";
0490 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0491 interrupt-parent = <&spi_l2_intc>;
0492 interrupt-names = "spi_lr_fullness_reached",
0493 "spi_lr_session_aborted",
0494 "spi_lr_impatient",
0495 "spi_lr_session_done",
0496 "spi_lr_overread",
0497 "mspi_done",
0498 "mspi_halted";
0499 status = "disabled";
0500 };
0501
0502 mspi: spi@409200 {
0503 #address-cells = <1>;
0504 #size-cells = <0>;
0505 compatible = "brcm,spi-bcm-qspi",
0506 "brcm,spi-brcmstb-mspi";
0507 clocks = <&upg_clk>;
0508 reg = <0x409200 0x180>;
0509 reg-names = "mspi";
0510 interrupts = <0x14>;
0511 interrupt-parent = <&upg_aon_irq0_intc>;
0512 interrupt-names = "mspi_done";
0513 status = "disabled";
0514 };
0515
0516 waketimer: waketimer@409580 {
0517 compatible = "brcm,brcmstb-waketimer";
0518 reg = <0x409580 0x14>;
0519 interrupts = <0x3>;
0520 interrupt-parent = <&aon_pm_l2_intc>;
0521 interrupt-names = "timer";
0522 clocks = <&upg_clk>;
0523 status = "disabled";
0524 };
0525 };
0526
0527 memory_controllers {
0528 compatible = "simple-bus";
0529 ranges = <0x0 0x103b0000 0x1a000>;
0530 #address-cells = <1>;
0531 #size-cells = <1>;
0532
0533 memory-controller@0 {
0534 compatible = "brcm,brcmstb-memc", "simple-bus";
0535 ranges = <0x0 0x0 0xa000>;
0536 #address-cells = <1>;
0537 #size-cells = <1>;
0538
0539 memc-arb@1000 {
0540 compatible = "brcm,brcmstb-memc-arb";
0541 reg = <0x1000 0x248>;
0542 };
0543
0544 memc-ddr@2000 {
0545 compatible = "brcm,brcmstb-memc-ddr";
0546 reg = <0x2000 0x300>;
0547 };
0548
0549 ddr-phy@6000 {
0550 compatible = "brcm,brcmstb-ddr-phy";
0551 reg = <0x6000 0xc8>;
0552 };
0553
0554 shimphy@8000 {
0555 compatible = "brcm,brcmstb-ddr-shimphy";
0556 reg = <0x8000 0x13c>;
0557 };
0558 };
0559
0560 memory-controller@1 {
0561 compatible = "brcm,brcmstb-memc", "simple-bus";
0562 ranges = <0x0 0x10000 0xa000>;
0563 #address-cells = <1>;
0564 #size-cells = <1>;
0565
0566 memc-arb@1000 {
0567 compatible = "brcm,brcmstb-memc-arb";
0568 reg = <0x1000 0x248>;
0569 };
0570
0571 memc-ddr@2000 {
0572 compatible = "brcm,brcmstb-memc-ddr";
0573 reg = <0x2000 0x300>;
0574 };
0575
0576 ddr-phy@6000 {
0577 compatible = "brcm,brcmstb-ddr-phy";
0578 reg = <0x6000 0xc8>;
0579 };
0580
0581 shimphy@8000 {
0582 compatible = "brcm,brcmstb-ddr-shimphy";
0583 reg = <0x8000 0x13c>;
0584 };
0585 };
0586 };
0587
0588 pcie_0: pcie@8b20000 {
0589 status = "disabled";
0590 compatible = "brcm,bcm7425-pcie";
0591
0592 ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
0593 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
0594 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
0595 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
0596
0597 reg = <0x10410000 0x19310>;
0598 aspm-no-l0s;
0599 device_type = "pci";
0600 msi-controller;
0601 msi-parent = <&pcie_0>;
0602 #address-cells = <0x3>;
0603 #size-cells = <0x2>;
0604 bus-range = <0x0 0xff>;
0605 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0606 linux,pci-domain = <0x0>;
0607
0608 interrupt-parent = <&periph_intc>;
0609 interrupts = <37>, <37>;
0610 interrupt-names = "pcie", "msi";
0611 #interrupt-cells = <0x1>;
0612 interrupt-map = <0 0 0 1 &periph_intc 0x21
0613 0 0 0 1 &periph_intc 0x22
0614 0 0 0 1 &periph_intc 0x23
0615 0 0 0 1 &periph_intc 0x24>;
0616 };
0617 };
