0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7420";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <93750000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips5000";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018
0019 cpu@1 {
0020 compatible = "brcm,bmips5000";
0021 device_type = "cpu";
0022 reg = <1>;
0023 };
0024 };
0025
0026 aliases {
0027 uart0 = &uart0;
0028 };
0029
0030 cpu_intc: interrupt-controller {
0031 #address-cells = <0>;
0032 compatible = "mti,cpu-interrupt-controller";
0033
0034 interrupt-controller;
0035 #interrupt-cells = <1>;
0036 };
0037
0038 clocks {
0039 uart_clk: uart_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <81000000>;
0043 };
0044
0045 upg_clk: upg_clk {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <27000000>;
0049 };
0050 };
0051
0052 rdb {
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 compatible = "simple-bus";
0057 ranges = <0 0x10000000 0x01000000>;
0058
0059 periph_intc: interrupt-controller@441400 {
0060 compatible = "brcm,bcm7038-l1-intc";
0061 reg = <0x441400 0x30>, <0x441600 0x30>;
0062
0063 interrupt-controller;
0064 #interrupt-cells = <1>;
0065
0066 interrupt-parent = <&cpu_intc>;
0067 interrupts = <2>, <3>;
0068 };
0069
0070 sun_l2_intc: interrupt-controller@401800 {
0071 compatible = "brcm,l2-intc";
0072 reg = <0x401800 0x30>;
0073 interrupt-controller;
0074 #interrupt-cells = <1>;
0075 interrupt-parent = <&periph_intc>;
0076 interrupts = <23>;
0077 };
0078
0079 gisb-arb@400000 {
0080 compatible = "brcm,bcm7400-gisb-arb";
0081 reg = <0x400000 0xdc>;
0082 native-endian;
0083 interrupt-parent = <&sun_l2_intc>;
0084 interrupts = <0>, <2>;
0085 brcm,gisb-arb-master-mask = <0x3ff>;
0086 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
0087 "pcie_0", "bsp_0", "rdc_0",
0088 "rptd_0", "avd_0", "avd_1",
0089 "jtag_0";
0090 };
0091
0092 upg_irq0_intc: interrupt-controller@406780 {
0093 compatible = "brcm,bcm7120-l2-intc";
0094 reg = <0x406780 0x8>;
0095
0096 brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
0097 brcm,int-fwd-mask = <0x70000>;
0098
0099 interrupt-controller;
0100 #interrupt-cells = <1>;
0101
0102 interrupt-parent = <&periph_intc>;
0103 interrupts = <18>, <19>, <20>;
0104 interrupt-names = "upg_main", "upg_bsc", "upg_spi";
0105 };
0106
0107 sun_top_ctrl: syscon@404000 {
0108 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
0109 reg = <0x404000 0x60c>;
0110 native-endian;
0111 };
0112
0113 reboot {
0114 compatible = "brcm,bcm7038-reboot";
0115 syscon = <&sun_top_ctrl 0x8 0x14>;
0116 };
0117
0118 uart0: serial@406b00 {
0119 compatible = "ns16550a";
0120 reg = <0x406b00 0x20>;
0121 reg-io-width = <0x4>;
0122 reg-shift = <0x2>;
0123 interrupt-parent = <&periph_intc>;
0124 interrupts = <21>;
0125 clocks = <&uart_clk>;
0126 status = "disabled";
0127 };
0128
0129 uart1: serial@406b40 {
0130 compatible = "ns16550a";
0131 reg = <0x406b40 0x20>;
0132 reg-io-width = <0x4>;
0133 reg-shift = <0x2>;
0134 interrupt-parent = <&periph_intc>;
0135 interrupts = <64>;
0136 clocks = <&uart_clk>;
0137 status = "disabled";
0138 };
0139
0140 uart2: serial@406b80 {
0141 compatible = "ns16550a";
0142 reg = <0x406b80 0x20>;
0143 reg-io-width = <0x4>;
0144 reg-shift = <0x2>;
0145 interrupt-parent = <&periph_intc>;
0146 interrupts = <65>;
0147 clocks = <&uart_clk>;
0148 status = "disabled";
0149 };
0150
0151 bsca: i2c@406200 {
0152 clock-frequency = <390000>;
0153 compatible = "brcm,brcmstb-i2c";
0154 interrupt-parent = <&upg_irq0_intc>;
0155 reg = <0x406200 0x58>;
0156 interrupts = <24>;
0157 interrupt-names = "upg_bsca";
0158 status = "disabled";
0159 };
0160
0161 bscb: i2c@406280 {
0162 clock-frequency = <390000>;
0163 compatible = "brcm,brcmstb-i2c";
0164 interrupt-parent = <&upg_irq0_intc>;
0165 reg = <0x406280 0x58>;
0166 interrupts = <25>;
0167 interrupt-names = "upg_bscb";
0168 status = "disabled";
0169 };
0170
0171 bscc: i2c@406300 {
0172 clock-frequency = <390000>;
0173 compatible = "brcm,brcmstb-i2c";
0174 interrupt-parent = <&upg_irq0_intc>;
0175 reg = <0x406300 0x58>;
0176 interrupts = <26>;
0177 interrupt-names = "upg_bscc";
0178 status = "disabled";
0179 };
0180
0181 bscd: i2c@406380 {
0182 clock-frequency = <390000>;
0183 compatible = "brcm,brcmstb-i2c";
0184 interrupt-parent = <&upg_irq0_intc>;
0185 reg = <0x406380 0x58>;
0186 interrupts = <27>;
0187 interrupt-names = "upg_bscd";
0188 status = "disabled";
0189 };
0190
0191 bsce: i2c@406800 {
0192 clock-frequency = <390000>;
0193 compatible = "brcm,brcmstb-i2c";
0194 interrupt-parent = <&upg_irq0_intc>;
0195 reg = <0x406800 0x58>;
0196 interrupts = <28>;
0197 interrupt-names = "upg_bsce";
0198 status = "disabled";
0199 };
0200
0201 pwma: pwm@406580 {
0202 compatible = "brcm,bcm7038-pwm";
0203 reg = <0x406580 0x28>;
0204 #pwm-cells = <2>;
0205 clocks = <&upg_clk>;
0206 status = "disabled";
0207 };
0208
0209 pwmb: pwm@406880 {
0210 compatible = "brcm,bcm7038-pwm";
0211 reg = <0x406880 0x28>;
0212 #pwm-cells = <2>;
0213 clocks = <&upg_clk>;
0214 status = "disabled";
0215 };
0216
0217 watchdog: watchdog@4067e8 {
0218 clocks = <&upg_clk>;
0219 compatible = "brcm,bcm7038-wdt";
0220 reg = <0x4067e8 0x14>;
0221 status = "disabled";
0222 };
0223
0224 upg_gio: gpio@406700 {
0225 compatible = "brcm,brcmstb-gpio";
0226 reg = <0x406700 0x80>;
0227 #gpio-cells = <2>;
0228 #interrupt-cells = <2>;
0229 gpio-controller;
0230 interrupt-controller;
0231 interrupt-parent = <&upg_irq0_intc>;
0232 interrupts = <6>;
0233 brcm,gpio-bank-widths = <32 32 32 27>;
0234 };
0235
0236 enet0: ethernet@468000 {
0237 phy-mode = "internal";
0238 phy-handle = <&phy1>;
0239 mac-address = [ 00 10 18 36 23 1a ];
0240 compatible = "brcm,genet-v1";
0241 #address-cells = <0x1>;
0242 #size-cells = <0x1>;
0243 reg = <0x468000 0x3c8c>;
0244 interrupts = <69>, <79>;
0245 interrupt-parent = <&periph_intc>;
0246 status = "disabled";
0247
0248 mdio@e14 {
0249 compatible = "brcm,genet-mdio-v1";
0250 #address-cells = <0x1>;
0251 #size-cells = <0x0>;
0252 reg = <0xe14 0x8>;
0253
0254 phy1: ethernet-phy@1 {
0255 max-speed = <100>;
0256 reg = <0x1>;
0257 compatible = "brcm,65nm-ephy",
0258 "ethernet-phy-ieee802.3-c22";
0259 };
0260 };
0261 };
0262
0263 ehci0: usb@488300 {
0264 compatible = "brcm,bcm7420-ehci", "generic-ehci";
0265 reg = <0x488300 0x100>;
0266 interrupt-parent = <&periph_intc>;
0267 interrupts = <60>;
0268 status = "disabled";
0269 };
0270
0271 ohci0: usb@488400 {
0272 compatible = "brcm,bcm7420-ohci", "generic-ohci";
0273 reg = <0x488400 0x100>;
0274 native-endian;
0275 no-big-frame-no;
0276 interrupt-parent = <&periph_intc>;
0277 interrupts = <61>;
0278 status = "disabled";
0279 };
0280
0281 ehci1: usb@488500 {
0282 compatible = "brcm,bcm7420-ehci", "generic-ehci";
0283 reg = <0x488500 0x100>;
0284 interrupt-parent = <&periph_intc>;
0285 interrupts = <55>;
0286 status = "disabled";
0287 };
0288
0289 ohci1: usb@488600 {
0290 compatible = "brcm,bcm7420-ohci", "generic-ohci";
0291 reg = <0x488600 0x100>;
0292 native-endian;
0293 no-big-frame-no;
0294 interrupt-parent = <&periph_intc>;
0295 interrupts = <62>;
0296 status = "disabled";
0297 };
0298
0299 spi_l2_intc: interrupt-controller@411d00 {
0300 compatible = "brcm,l2-intc";
0301 reg = <0x411d00 0x30>;
0302 interrupt-controller;
0303 #interrupt-cells = <1>;
0304 interrupt-parent = <&periph_intc>;
0305 interrupts = <78>;
0306 };
0307
0308 qspi: spi@443000 {
0309 #address-cells = <0x1>;
0310 #size-cells = <0x0>;
0311 compatible = "brcm,spi-bcm-qspi",
0312 "brcm,spi-brcmstb-qspi";
0313 clocks = <&upg_clk>;
0314 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
0315 reg-names = "cs_reg", "hif_mspi", "bspi";
0316 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0317 interrupt-parent = <&spi_l2_intc>;
0318 interrupt-names = "spi_lr_fullness_reached",
0319 "spi_lr_session_aborted",
0320 "spi_lr_impatient",
0321 "spi_lr_session_done",
0322 "spi_lr_overread",
0323 "mspi_done",
0324 "mspi_halted";
0325 status = "disabled";
0326 };
0327
0328 mspi: spi@406400 {
0329 #address-cells = <1>;
0330 #size-cells = <0>;
0331 compatible = "brcm,spi-bcm-qspi",
0332 "brcm,spi-brcmstb-mspi";
0333 clocks = <&upg_clk>;
0334 reg = <0x406400 0x180>;
0335 reg-names = "mspi";
0336 interrupts = <0x14>;
0337 interrupt-parent = <&upg_irq0_intc>;
0338 interrupt-names = "mspi_done";
0339 status = "disabled";
0340 };
0341 };
0342 };
