0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7362";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <375000000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips4380";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018
0019 cpu@1 {
0020 compatible = "brcm,bmips4380";
0021 device_type = "cpu";
0022 reg = <1>;
0023 };
0024 };
0025
0026 aliases {
0027 uart0 = &uart0;
0028 };
0029
0030 cpu_intc: interrupt-controller {
0031 #address-cells = <0>;
0032 compatible = "mti,cpu-interrupt-controller";
0033
0034 interrupt-controller;
0035 #interrupt-cells = <1>;
0036 };
0037
0038 clocks {
0039 uart_clk: uart_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <81000000>;
0043 };
0044
0045 upg_clk: upg_clk {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <27000000>;
0049 };
0050 };
0051
0052 rdb {
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 compatible = "simple-bus";
0057 ranges = <0 0x10000000 0x01000000>;
0058
0059 periph_intc: interrupt-controller@411400 {
0060 compatible = "brcm,bcm7038-l1-intc";
0061 reg = <0x411400 0x30>, <0x411600 0x30>;
0062
0063 interrupt-controller;
0064 #interrupt-cells = <1>;
0065
0066 interrupt-parent = <&cpu_intc>;
0067 interrupts = <2>, <3>;
0068 };
0069
0070 sun_l2_intc: interrupt-controller@403000 {
0071 compatible = "brcm,l2-intc";
0072 reg = <0x403000 0x30>;
0073 interrupt-controller;
0074 #interrupt-cells = <1>;
0075 interrupt-parent = <&periph_intc>;
0076 interrupts = <48>;
0077 };
0078
0079 gisb-arb@400000 {
0080 compatible = "brcm,bcm7400-gisb-arb";
0081 reg = <0x400000 0xdc>;
0082 native-endian;
0083 interrupt-parent = <&sun_l2_intc>;
0084 interrupts = <0>, <2>;
0085 brcm,gisb-arb-master-mask = <0x2f3>;
0086 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
0087 "rdc_0", "raaga_0",
0088 "avd_0", "jtag_0";
0089 };
0090
0091 upg_irq0_intc: interrupt-controller@406600 {
0092 compatible = "brcm,bcm7120-l2-intc";
0093 reg = <0x406600 0x8>;
0094
0095 brcm,int-map-mask = <0x44>, <0x7000000>;
0096 brcm,int-fwd-mask = <0x70000>;
0097
0098 interrupt-controller;
0099 #interrupt-cells = <1>;
0100
0101 interrupt-parent = <&periph_intc>;
0102 interrupts = <56>, <54>;
0103 interrupt-names = "upg_main", "upg_bsc";
0104 };
0105
0106 upg_aon_irq0_intc: interrupt-controller@408b80 {
0107 compatible = "brcm,bcm7120-l2-intc";
0108 reg = <0x408b80 0x8>;
0109
0110 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
0111 brcm,int-fwd-mask = <0>;
0112 brcm,irq-can-wake;
0113
0114 interrupt-controller;
0115 #interrupt-cells = <1>;
0116
0117 interrupt-parent = <&periph_intc>;
0118 interrupts = <57>, <55>, <59>;
0119 interrupt-names = "upg_main_aon", "upg_bsc_aon",
0120 "upg_spi";
0121 };
0122
0123 sun_top_ctrl: syscon@404000 {
0124 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
0125 reg = <0x404000 0x51c>;
0126 native-endian;
0127 };
0128
0129 reboot {
0130 compatible = "brcm,brcmstb-reboot";
0131 syscon = <&sun_top_ctrl 0x304 0x308>;
0132 };
0133
0134 uart0: serial@406800 {
0135 compatible = "ns16550a";
0136 reg = <0x406800 0x20>;
0137 reg-io-width = <0x4>;
0138 reg-shift = <0x2>;
0139 native-endian;
0140 interrupt-parent = <&periph_intc>;
0141 interrupts = <61>;
0142 clocks = <&uart_clk>;
0143 status = "disabled";
0144 };
0145
0146 uart1: serial@406840 {
0147 compatible = "ns16550a";
0148 reg = <0x406840 0x20>;
0149 reg-io-width = <0x4>;
0150 reg-shift = <0x2>;
0151 native-endian;
0152 interrupt-parent = <&periph_intc>;
0153 interrupts = <62>;
0154 clocks = <&uart_clk>;
0155 status = "disabled";
0156 };
0157
0158 uart2: serial@406880 {
0159 compatible = "ns16550a";
0160 reg = <0x406880 0x20>;
0161 reg-io-width = <0x4>;
0162 reg-shift = <0x2>;
0163 native-endian;
0164 interrupt-parent = <&periph_intc>;
0165 interrupts = <63>;
0166 clocks = <&uart_clk>;
0167 status = "disabled";
0168 };
0169
0170 bsca: i2c@406200 {
0171 clock-frequency = <390000>;
0172 compatible = "brcm,brcmstb-i2c";
0173 interrupt-parent = <&upg_irq0_intc>;
0174 reg = <0x406200 0x58>;
0175 interrupts = <24>;
0176 interrupt-names = "upg_bsca";
0177 status = "disabled";
0178 };
0179
0180 bscb: i2c@406280 {
0181 clock-frequency = <390000>;
0182 compatible = "brcm,brcmstb-i2c";
0183 interrupt-parent = <&upg_irq0_intc>;
0184 reg = <0x406280 0x58>;
0185 interrupts = <25>;
0186 interrupt-names = "upg_bscb";
0187 status = "disabled";
0188 };
0189
0190 bscd: i2c@408980 {
0191 clock-frequency = <390000>;
0192 compatible = "brcm,brcmstb-i2c";
0193 interrupt-parent = <&upg_aon_irq0_intc>;
0194 reg = <0x408980 0x58>;
0195 interrupts = <27>;
0196 interrupt-names = "upg_bscd";
0197 status = "disabled";
0198 };
0199
0200 pwma: pwm@406400 {
0201 compatible = "brcm,bcm7038-pwm";
0202 reg = <0x406400 0x28>;
0203 #pwm-cells = <2>;
0204 clocks = <&upg_clk>;
0205 status = "disabled";
0206 };
0207
0208 watchdog: watchdog@4066a8 {
0209 clocks = <&upg_clk>;
0210 compatible = "brcm,bcm7038-wdt";
0211 reg = <0x4066a8 0x14>;
0212 status = "disabled";
0213 };
0214
0215 aon_pm_l2_intc: interrupt-controller@408440 {
0216 compatible = "brcm,l2-intc";
0217 reg = <0x408440 0x30>;
0218 interrupt-controller;
0219 #interrupt-cells = <1>;
0220 interrupt-parent = <&periph_intc>;
0221 interrupts = <50>;
0222 brcm,irq-can-wake;
0223 };
0224
0225 aon_ctrl: syscon@408000 {
0226 compatible = "brcm,brcmstb-aon-ctrl";
0227 reg = <0x408000 0x100>, <0x408200 0x200>;
0228 reg-names = "aon-ctrl", "aon-sram";
0229 };
0230
0231 timers: timer@406680 {
0232 compatible = "brcm,brcmstb-timers";
0233 reg = <0x406680 0x40>;
0234 };
0235
0236 upg_gio: gpio@406500 {
0237 compatible = "brcm,brcmstb-gpio";
0238 reg = <0x406500 0xa0>;
0239 #gpio-cells = <2>;
0240 #interrupt-cells = <2>;
0241 gpio-controller;
0242 interrupt-controller;
0243 interrupt-parent = <&upg_irq0_intc>;
0244 interrupts = <6>;
0245 brcm,gpio-bank-widths = <32 32 32 29 4>;
0246 };
0247
0248 upg_gio_aon: gpio@408c00 {
0249 compatible = "brcm,brcmstb-gpio";
0250 reg = <0x408c00 0x60>;
0251 #gpio-cells = <2>;
0252 #interrupt-cells = <2>;
0253 gpio-controller;
0254 interrupt-controller;
0255 interrupt-parent = <&upg_aon_irq0_intc>;
0256 interrupts = <6>;
0257 interrupts-extended = <&upg_aon_irq0_intc 6>,
0258 <&aon_pm_l2_intc 5>;
0259 wakeup-source;
0260 brcm,gpio-bank-widths = <21 32 2>;
0261 };
0262
0263 enet0: ethernet@430000 {
0264 phy-mode = "internal";
0265 phy-handle = <&phy1>;
0266 mac-address = [ 00 10 18 36 23 1a ];
0267 compatible = "brcm,genet-v2";
0268 #address-cells = <0x1>;
0269 #size-cells = <0x1>;
0270 reg = <0x430000 0x4c8c>;
0271 interrupts = <24>, <25>;
0272 interrupt-parent = <&periph_intc>;
0273 status = "disabled";
0274
0275 mdio@e14 {
0276 compatible = "brcm,genet-mdio-v2";
0277 #address-cells = <0x1>;
0278 #size-cells = <0x0>;
0279 reg = <0xe14 0x8>;
0280
0281 phy1: ethernet-phy@1 {
0282 max-speed = <100>;
0283 reg = <0x1>;
0284 compatible = "brcm,40nm-ephy",
0285 "ethernet-phy-ieee802.3-c22";
0286 };
0287 };
0288 };
0289
0290 ehci0: usb@480300 {
0291 compatible = "brcm,bcm7362-ehci", "generic-ehci";
0292 reg = <0x480300 0x100>;
0293 native-endian;
0294 interrupt-parent = <&periph_intc>;
0295 interrupts = <65>;
0296 status = "disabled";
0297 };
0298
0299 ohci0: usb@480400 {
0300 compatible = "brcm,bcm7362-ohci", "generic-ohci";
0301 reg = <0x480400 0x100>;
0302 native-endian;
0303 no-big-frame-no;
0304 interrupt-parent = <&periph_intc>;
0305 interrupts = <66>;
0306 status = "disabled";
0307 };
0308
0309 hif_l2_intc: interrupt-controller@411000 {
0310 compatible = "brcm,l2-intc";
0311 reg = <0x411000 0x30>;
0312 interrupt-controller;
0313 #interrupt-cells = <1>;
0314 interrupt-parent = <&periph_intc>;
0315 interrupts = <30>;
0316 };
0317
0318 nand: nand@412800 {
0319 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
0320 #address-cells = <1>;
0321 #size-cells = <0>;
0322 reg-names = "nand";
0323 reg = <0x412800 0x400>;
0324 interrupt-parent = <&hif_l2_intc>;
0325 interrupts = <24>;
0326 status = "disabled";
0327 };
0328
0329 sata: sata@181000 {
0330 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
0331 reg-names = "ahci", "top-ctrl";
0332 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
0333 interrupt-parent = <&periph_intc>;
0334 interrupts = <86>;
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337 status = "disabled";
0338
0339 sata0: sata-port@0 {
0340 reg = <0>;
0341 phys = <&sata_phy0>;
0342 };
0343
0344 sata1: sata-port@1 {
0345 reg = <1>;
0346 phys = <&sata_phy1>;
0347 };
0348 };
0349
0350 sata_phy: sata-phy@180100 {
0351 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
0352 reg = <0x180100 0x0eff>;
0353 reg-names = "phy";
0354 #address-cells = <1>;
0355 #size-cells = <0>;
0356 status = "disabled";
0357
0358 sata_phy0: sata-phy@0 {
0359 reg = <0>;
0360 #phy-cells = <0>;
0361 };
0362
0363 sata_phy1: sata-phy@1 {
0364 reg = <1>;
0365 #phy-cells = <0>;
0366 };
0367 };
0368
0369 sdhci0: sdhci@410000 {
0370 compatible = "brcm,bcm7425-sdhci";
0371 reg = <0x410000 0x100>;
0372 interrupt-parent = <&periph_intc>;
0373 interrupts = <82>;
0374 status = "disabled";
0375 };
0376
0377 spi_l2_intc: interrupt-controller@411d00 {
0378 compatible = "brcm,l2-intc";
0379 reg = <0x411d00 0x30>;
0380 interrupt-controller;
0381 #interrupt-cells = <1>;
0382 interrupt-parent = <&periph_intc>;
0383 interrupts = <31>;
0384 };
0385
0386 qspi: spi@413000 {
0387 #address-cells = <0x1>;
0388 #size-cells = <0x0>;
0389 compatible = "brcm,spi-bcm-qspi",
0390 "brcm,spi-brcmstb-qspi";
0391 clocks = <&upg_clk>;
0392 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
0393 reg-names = "cs_reg", "hif_mspi", "bspi";
0394 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0395 interrupt-parent = <&spi_l2_intc>;
0396 interrupt-names = "spi_lr_fullness_reached",
0397 "spi_lr_session_aborted",
0398 "spi_lr_impatient",
0399 "spi_lr_session_done",
0400 "spi_lr_overread",
0401 "mspi_done",
0402 "mspi_halted";
0403 status = "disabled";
0404 };
0405
0406 mspi: spi@408a00 {
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409 compatible = "brcm,spi-bcm-qspi",
0410 "brcm,spi-brcmstb-mspi";
0411 clocks = <&upg_clk>;
0412 reg = <0x408a00 0x180>;
0413 reg-names = "mspi";
0414 interrupts = <0x14>;
0415 interrupt-parent = <&upg_aon_irq0_intc>;
0416 interrupt-names = "mspi_done";
0417 status = "disabled";
0418 };
0419
0420 waketimer: waketimer@408e80 {
0421 compatible = "brcm,brcmstb-waketimer";
0422 reg = <0x408e80 0x14>;
0423 interrupts = <0x3>;
0424 interrupt-parent = <&aon_pm_l2_intc>;
0425 interrupt-names = "timer";
0426 clocks = <&upg_clk>;
0427 status = "disabled";
0428 };
0429 };
0430
0431 memory_controllers {
0432 compatible = "simple-bus";
0433 ranges = <0x0 0x103b0000 0xa000>;
0434 #address-cells = <1>;
0435 #size-cells = <1>;
0436
0437 memory-controller@0 {
0438 compatible = "brcm,brcmstb-memc", "simple-bus";
0439 ranges = <0x0 0x0 0xa000>;
0440 #address-cells = <1>;
0441 #size-cells = <1>;
0442
0443 memc-arb@1000 {
0444 compatible = "brcm,brcmstb-memc-arb";
0445 reg = <0x1000 0x248>;
0446 };
0447
0448 memc-ddr@2000 {
0449 compatible = "brcm,brcmstb-memc-ddr";
0450 reg = <0x2000 0x300>;
0451 };
0452
0453 ddr-phy@6000 {
0454 compatible = "brcm,brcmstb-ddr-phy";
0455 reg = <0x6000 0xc8>;
0456 };
0457
0458 shimphy@8000 {
0459 compatible = "brcm,brcmstb-ddr-shimphy";
0460 reg = <0x8000 0x13c>;
0461 };
0462 };
0463 };
0464 };
