0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7360";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <375000000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips3300";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018 };
0019
0020 aliases {
0021 uart0 = &uart0;
0022 };
0023
0024 cpu_intc: interrupt-controller {
0025 #address-cells = <0>;
0026 compatible = "mti,cpu-interrupt-controller";
0027
0028 interrupt-controller;
0029 #interrupt-cells = <1>;
0030 };
0031
0032 clocks {
0033 uart_clk: uart_clk {
0034 compatible = "fixed-clock";
0035 #clock-cells = <0>;
0036 clock-frequency = <81000000>;
0037 };
0038
0039 upg_clk: upg_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <27000000>;
0043 };
0044 };
0045
0046 rdb {
0047 #address-cells = <1>;
0048 #size-cells = <1>;
0049
0050 compatible = "simple-bus";
0051 ranges = <0 0x10000000 0x01000000>;
0052
0053 periph_intc: interrupt-controller@411400 {
0054 compatible = "brcm,bcm7038-l1-intc";
0055 reg = <0x411400 0x30>;
0056
0057 interrupt-controller;
0058 #interrupt-cells = <1>;
0059
0060 interrupt-parent = <&cpu_intc>;
0061 interrupts = <2>;
0062 };
0063
0064 sun_l2_intc: interrupt-controller@403000 {
0065 compatible = "brcm,l2-intc";
0066 reg = <0x403000 0x30>;
0067 interrupt-controller;
0068 #interrupt-cells = <1>;
0069 interrupt-parent = <&periph_intc>;
0070 interrupts = <48>;
0071 };
0072
0073 gisb-arb@400000 {
0074 compatible = "brcm,bcm7400-gisb-arb";
0075 reg = <0x400000 0xdc>;
0076 native-endian;
0077 interrupt-parent = <&sun_l2_intc>;
0078 interrupts = <0>, <2>;
0079 brcm,gisb-arb-master-mask = <0x2f3>;
0080 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
0081 "rdc_0", "raaga_0",
0082 "avd_0", "jtag_0";
0083 };
0084
0085 upg_irq0_intc: interrupt-controller@406600 {
0086 compatible = "brcm,bcm7120-l2-intc";
0087 reg = <0x406600 0x8>;
0088
0089 brcm,int-map-mask = <0x44>, <0x7000000>;
0090 brcm,int-fwd-mask = <0x70000>;
0091
0092 interrupt-controller;
0093 #interrupt-cells = <1>;
0094
0095 interrupt-parent = <&periph_intc>;
0096 interrupts = <56>, <54>;
0097 interrupt-names = "upg_main", "upg_bsc";
0098 };
0099
0100 upg_aon_irq0_intc: interrupt-controller@408b80 {
0101 compatible = "brcm,bcm7120-l2-intc";
0102 reg = <0x408b80 0x8>;
0103
0104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
0105 brcm,int-fwd-mask = <0>;
0106 brcm,irq-can-wake;
0107
0108 interrupt-controller;
0109 #interrupt-cells = <1>;
0110
0111 interrupt-parent = <&periph_intc>;
0112 interrupts = <57>, <55>, <59>;
0113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
0114 "upg_spi";
0115 };
0116
0117 sun_top_ctrl: syscon@404000 {
0118 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
0119 reg = <0x404000 0x51c>;
0120 native-endian;
0121 };
0122
0123 reboot {
0124 compatible = "brcm,brcmstb-reboot";
0125 syscon = <&sun_top_ctrl 0x304 0x308>;
0126 };
0127
0128 uart0: serial@406800 {
0129 compatible = "ns16550a";
0130 reg = <0x406800 0x20>;
0131 reg-io-width = <0x4>;
0132 reg-shift = <0x2>;
0133 native-endian;
0134 interrupt-parent = <&periph_intc>;
0135 interrupts = <61>;
0136 clocks = <&uart_clk>;
0137 status = "disabled";
0138 };
0139
0140 uart1: serial@406840 {
0141 compatible = "ns16550a";
0142 reg = <0x406840 0x20>;
0143 reg-io-width = <0x4>;
0144 reg-shift = <0x2>;
0145 native-endian;
0146 interrupt-parent = <&periph_intc>;
0147 interrupts = <62>;
0148 clocks = <&uart_clk>;
0149 status = "disabled";
0150 };
0151
0152 uart2: serial@406880 {
0153 compatible = "ns16550a";
0154 reg = <0x406880 0x20>;
0155 reg-io-width = <0x4>;
0156 reg-shift = <0x2>;
0157 native-endian;
0158 interrupt-parent = <&periph_intc>;
0159 interrupts = <63>;
0160 clocks = <&uart_clk>;
0161 status = "disabled";
0162 };
0163
0164 bsca: i2c@406200 {
0165 clock-frequency = <390000>;
0166 compatible = "brcm,brcmstb-i2c";
0167 interrupt-parent = <&upg_irq0_intc>;
0168 reg = <0x406200 0x58>;
0169 interrupts = <24>;
0170 interrupt-names = "upg_bsca";
0171 status = "disabled";
0172 };
0173
0174 bscb: i2c@406280 {
0175 clock-frequency = <390000>;
0176 compatible = "brcm,brcmstb-i2c";
0177 interrupt-parent = <&upg_irq0_intc>;
0178 reg = <0x406280 0x58>;
0179 interrupts = <25>;
0180 interrupt-names = "upg_bscb";
0181 status = "disabled";
0182 };
0183
0184 bscc: i2c@406300 {
0185 clock-frequency = <390000>;
0186 compatible = "brcm,brcmstb-i2c";
0187 interrupt-parent = <&upg_irq0_intc>;
0188 reg = <0x406300 0x58>;
0189 interrupts = <26>;
0190 interrupt-names = "upg_bscc";
0191 status = "disabled";
0192 };
0193
0194 bscd: i2c@408980 {
0195 clock-frequency = <390000>;
0196 compatible = "brcm,brcmstb-i2c";
0197 interrupt-parent = <&upg_aon_irq0_intc>;
0198 reg = <0x408980 0x58>;
0199 interrupts = <27>;
0200 interrupt-names = "upg_bscd";
0201 status = "disabled";
0202 };
0203
0204 pwma: pwm@406400 {
0205 compatible = "brcm,bcm7038-pwm";
0206 reg = <0x406400 0x28>;
0207 #pwm-cells = <2>;
0208 clocks = <&upg_clk>;
0209 status = "disabled";
0210 };
0211
0212 watchdog: watchdog@4066a8 {
0213 clocks = <&upg_clk>;
0214 compatible = "brcm,bcm7038-wdt";
0215 reg = <0x4066a8 0x14>;
0216 status = "disabled";
0217 };
0218
0219 aon_pm_l2_intc: interrupt-controller@408440 {
0220 compatible = "brcm,l2-intc";
0221 reg = <0x408440 0x30>;
0222 interrupt-controller;
0223 #interrupt-cells = <1>;
0224 interrupt-parent = <&periph_intc>;
0225 interrupts = <50>;
0226 brcm,irq-can-wake;
0227 };
0228
0229 aon_ctrl: syscon@408000 {
0230 compatible = "brcm,brcmstb-aon-ctrl";
0231 reg = <0x408000 0x100>, <0x408200 0x200>;
0232 reg-names = "aon-ctrl", "aon-sram";
0233 };
0234
0235 timers: timer@406680 {
0236 compatible = "brcm,brcmstb-timers";
0237 reg = <0x406680 0x40>;
0238 };
0239
0240 upg_gio: gpio@406500 {
0241 compatible = "brcm,brcmstb-gpio";
0242 reg = <0x406500 0xa0>;
0243 #gpio-cells = <2>;
0244 #interrupt-cells = <2>;
0245 gpio-controller;
0246 interrupt-controller;
0247 interrupt-parent = <&upg_irq0_intc>;
0248 interrupts = <6>;
0249 brcm,gpio-bank-widths = <32 32 32 29 4>;
0250 };
0251
0252 upg_gio_aon: gpio@408c00 {
0253 compatible = "brcm,brcmstb-gpio";
0254 reg = <0x408c00 0x60>;
0255 #gpio-cells = <2>;
0256 #interrupt-cells = <2>;
0257 gpio-controller;
0258 interrupt-controller;
0259 interrupt-parent = <&upg_aon_irq0_intc>;
0260 interrupts = <6>;
0261 interrupts-extended = <&upg_aon_irq0_intc 6>,
0262 <&aon_pm_l2_intc 5>;
0263 wakeup-source;
0264 brcm,gpio-bank-widths = <21 32 2>;
0265 };
0266
0267 enet0: ethernet@430000 {
0268 phy-mode = "internal";
0269 phy-handle = <&phy1>;
0270 mac-address = [ 00 10 18 36 23 1a ];
0271 compatible = "brcm,genet-v2";
0272 #address-cells = <0x1>;
0273 #size-cells = <0x1>;
0274 reg = <0x430000 0x4c8c>;
0275 interrupts = <24>, <25>;
0276 interrupt-parent = <&periph_intc>;
0277 status = "disabled";
0278
0279 mdio@e14 {
0280 compatible = "brcm,genet-mdio-v2";
0281 #address-cells = <0x1>;
0282 #size-cells = <0x0>;
0283 reg = <0xe14 0x8>;
0284
0285 phy1: ethernet-phy@1 {
0286 max-speed = <100>;
0287 reg = <0x1>;
0288 compatible = "brcm,40nm-ephy",
0289 "ethernet-phy-ieee802.3-c22";
0290 };
0291 };
0292 };
0293
0294 ehci0: usb@480300 {
0295 compatible = "brcm,bcm7360-ehci", "generic-ehci";
0296 reg = <0x480300 0x100>;
0297 native-endian;
0298 interrupt-parent = <&periph_intc>;
0299 interrupts = <65>;
0300 status = "disabled";
0301 };
0302
0303 ohci0: usb@480400 {
0304 compatible = "brcm,bcm7360-ohci", "generic-ohci";
0305 reg = <0x480400 0x100>;
0306 native-endian;
0307 no-big-frame-no;
0308 interrupt-parent = <&periph_intc>;
0309 interrupts = <66>;
0310 status = "disabled";
0311 };
0312
0313 hif_l2_intc: interrupt-controller@411000 {
0314 compatible = "brcm,l2-intc";
0315 reg = <0x411000 0x30>;
0316 interrupt-controller;
0317 #interrupt-cells = <1>;
0318 interrupt-parent = <&periph_intc>;
0319 interrupts = <30>;
0320 };
0321
0322 nand: nand@412800 {
0323 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
0324 #address-cells = <1>;
0325 #size-cells = <0>;
0326 reg-names = "nand";
0327 reg = <0x412800 0x400>;
0328 interrupt-parent = <&hif_l2_intc>;
0329 interrupts = <24>;
0330 status = "disabled";
0331 };
0332
0333 sata: sata@181000 {
0334 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
0335 reg-names = "ahci", "top-ctrl";
0336 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
0337 interrupt-parent = <&periph_intc>;
0338 interrupts = <86>;
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 status = "disabled";
0342
0343 sata0: sata-port@0 {
0344 reg = <0>;
0345 phys = <&sata_phy0>;
0346 };
0347
0348 sata1: sata-port@1 {
0349 reg = <1>;
0350 phys = <&sata_phy1>;
0351 };
0352 };
0353
0354 sata_phy: sata-phy@180100 {
0355 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
0356 reg = <0x180100 0x0eff>;
0357 reg-names = "phy";
0358 #address-cells = <1>;
0359 #size-cells = <0>;
0360 status = "disabled";
0361
0362 sata_phy0: sata-phy@0 {
0363 reg = <0>;
0364 #phy-cells = <0>;
0365 };
0366
0367 sata_phy1: sata-phy@1 {
0368 reg = <1>;
0369 #phy-cells = <0>;
0370 };
0371 };
0372
0373 sdhci0: sdhci@410000 {
0374 compatible = "brcm,bcm7425-sdhci";
0375 reg = <0x410000 0x100>;
0376 interrupt-parent = <&periph_intc>;
0377 interrupts = <82>;
0378 status = "disabled";
0379 };
0380
0381 spi_l2_intc: interrupt-controller@411d00 {
0382 compatible = "brcm,l2-intc";
0383 reg = <0x411d00 0x30>;
0384 interrupt-controller;
0385 #interrupt-cells = <1>;
0386 interrupt-parent = <&periph_intc>;
0387 interrupts = <31>;
0388 };
0389
0390 qspi: spi@413000 {
0391 #address-cells = <0x1>;
0392 #size-cells = <0x0>;
0393 compatible = "brcm,spi-bcm-qspi",
0394 "brcm,spi-brcmstb-qspi";
0395 clocks = <&upg_clk>;
0396 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
0397 reg-names = "cs_reg", "hif_mspi", "bspi";
0398 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0399 interrupt-parent = <&spi_l2_intc>;
0400 interrupt-names = "spi_lr_fullness_reached",
0401 "spi_lr_session_aborted",
0402 "spi_lr_impatient",
0403 "spi_lr_session_done",
0404 "spi_lr_overread",
0405 "mspi_done",
0406 "mspi_halted";
0407 status = "disabled";
0408 };
0409
0410 mspi: spi@408a00 {
0411 #address-cells = <1>;
0412 #size-cells = <0>;
0413 compatible = "brcm,spi-bcm-qspi",
0414 "brcm,spi-brcmstb-mspi";
0415 clocks = <&upg_clk>;
0416 reg = <0x408a00 0x180>;
0417 reg-names = "mspi";
0418 interrupts = <0x14>;
0419 interrupt-parent = <&upg_aon_irq0_intc>;
0420 interrupt-names = "mspi_done";
0421 status = "disabled";
0422 };
0423
0424 waketimer: waketimer@408e80 {
0425 compatible = "brcm,brcmstb-waketimer";
0426 reg = <0x408e80 0x14>;
0427 interrupts = <0x3>;
0428 interrupt-parent = <&aon_pm_l2_intc>;
0429 interrupt-names = "timer";
0430 clocks = <&upg_clk>;
0431 status = "disabled";
0432 };
0433 };
0434
0435 memory_controllers {
0436 compatible = "simple-bus";
0437 ranges = <0x0 0x103b0000 0xa000>;
0438 #address-cells = <1>;
0439 #size-cells = <1>;
0440
0441 memory-controller@0 {
0442 compatible = "brcm,brcmstb-memc", "simple-bus";
0443 ranges = <0x0 0x0 0xa000>;
0444 #address-cells = <1>;
0445 #size-cells = <1>;
0446
0447 memc-arb@1000 {
0448 compatible = "brcm,brcmstb-memc-arb";
0449 reg = <0x1000 0x248>;
0450 };
0451
0452 memc-ddr@2000 {
0453 compatible = "brcm,brcmstb-memc-ddr";
0454 reg = <0x2000 0x300>;
0455 };
0456
0457 ddr-phy@6000 {
0458 compatible = "brcm,brcmstb-ddr-phy";
0459 reg = <0x6000 0xc8>;
0460 };
0461
0462 shimphy@8000 {
0463 compatible = "brcm,brcmstb-ddr-shimphy";
0464 reg = <0x8000 0x13c>;
0465 };
0466 };
0467 };
0468 };
