0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7358";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <375000000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips3300";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018 };
0019
0020 aliases {
0021 uart0 = &uart0;
0022 };
0023
0024 cpu_intc: interrupt-controller {
0025 #address-cells = <0>;
0026 compatible = "mti,cpu-interrupt-controller";
0027
0028 interrupt-controller;
0029 #interrupt-cells = <1>;
0030 };
0031
0032 clocks {
0033 uart_clk: uart_clk {
0034 compatible = "fixed-clock";
0035 #clock-cells = <0>;
0036 clock-frequency = <81000000>;
0037 };
0038
0039 upg_clk: upg_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <27000000>;
0043 };
0044 };
0045
0046 rdb {
0047 #address-cells = <1>;
0048 #size-cells = <1>;
0049
0050 compatible = "simple-bus";
0051 ranges = <0 0x10000000 0x01000000>;
0052
0053 periph_intc: interrupt-controller@411400 {
0054 compatible = "brcm,bcm7038-l1-intc";
0055 reg = <0x411400 0x30>;
0056
0057 interrupt-controller;
0058 #interrupt-cells = <1>;
0059
0060 interrupt-parent = <&cpu_intc>;
0061 interrupts = <2>;
0062 };
0063
0064 sun_l2_intc: interrupt-controller@403000 {
0065 compatible = "brcm,l2-intc";
0066 reg = <0x403000 0x30>;
0067 interrupt-controller;
0068 #interrupt-cells = <1>;
0069 interrupt-parent = <&periph_intc>;
0070 interrupts = <48>;
0071 };
0072
0073 gisb-arb@400000 {
0074 compatible = "brcm,bcm7400-gisb-arb";
0075 reg = <0x400000 0xdc>;
0076 native-endian;
0077 interrupt-parent = <&sun_l2_intc>;
0078 interrupts = <0>, <2>;
0079 brcm,gisb-arb-master-mask = <0x2f3>;
0080 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
0081 "rdc_0", "raaga_0",
0082 "avd_0", "jtag_0";
0083 };
0084
0085 upg_irq0_intc: interrupt-controller@406600 {
0086 compatible = "brcm,bcm7120-l2-intc";
0087 reg = <0x406600 0x8>;
0088
0089 brcm,int-map-mask = <0x44>, <0x7000000>;
0090 brcm,int-fwd-mask = <0x70000>;
0091
0092 interrupt-controller;
0093 #interrupt-cells = <1>;
0094
0095 interrupt-parent = <&periph_intc>;
0096 interrupts = <56>, <54>;
0097 interrupt-names = "upg_main", "upg_bsc";
0098 };
0099
0100 upg_aon_irq0_intc: interrupt-controller@408b80 {
0101 compatible = "brcm,bcm7120-l2-intc";
0102 reg = <0x408b80 0x8>;
0103
0104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
0105 brcm,int-fwd-mask = <0>;
0106 brcm,irq-can-wake;
0107
0108 interrupt-controller;
0109 #interrupt-cells = <1>;
0110
0111 interrupt-parent = <&periph_intc>;
0112 interrupts = <57>, <55>, <59>;
0113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
0114 "upg_spi";
0115 };
0116
0117 sun_top_ctrl: syscon@404000 {
0118 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
0119 reg = <0x404000 0x51c>;
0120 native-endian;
0121 };
0122
0123 reboot {
0124 compatible = "brcm,brcmstb-reboot";
0125 syscon = <&sun_top_ctrl 0x304 0x308>;
0126 };
0127
0128 uart0: serial@406800 {
0129 compatible = "ns16550a";
0130 reg = <0x406800 0x20>;
0131 reg-io-width = <0x4>;
0132 reg-shift = <0x2>;
0133 native-endian;
0134 interrupt-parent = <&periph_intc>;
0135 interrupts = <61>;
0136 clocks = <&uart_clk>;
0137 status = "disabled";
0138 };
0139
0140 uart1: serial@406840 {
0141 compatible = "ns16550a";
0142 reg = <0x406840 0x20>;
0143 reg-io-width = <0x4>;
0144 reg-shift = <0x2>;
0145 native-endian;
0146 interrupt-parent = <&periph_intc>;
0147 interrupts = <62>;
0148 clocks = <&uart_clk>;
0149 status = "disabled";
0150 };
0151
0152 uart2: serial@406880 {
0153 compatible = "ns16550a";
0154 reg = <0x406880 0x20>;
0155 reg-io-width = <0x4>;
0156 reg-shift = <0x2>;
0157 native-endian;
0158 interrupt-parent = <&periph_intc>;
0159 interrupts = <63>;
0160 clocks = <&uart_clk>;
0161 status = "disabled";
0162 };
0163
0164 bsca: i2c@406200 {
0165 clock-frequency = <390000>;
0166 compatible = "brcm,brcmstb-i2c";
0167 interrupt-parent = <&upg_irq0_intc>;
0168 reg = <0x406200 0x58>;
0169 interrupts = <24>;
0170 interrupt-names = "upg_bsca";
0171 status = "disabled";
0172 };
0173
0174 bscb: i2c@406280 {
0175 clock-frequency = <390000>;
0176 compatible = "brcm,brcmstb-i2c";
0177 interrupt-parent = <&upg_irq0_intc>;
0178 reg = <0x406280 0x58>;
0179 interrupts = <25>;
0180 interrupt-names = "upg_bscb";
0181 status = "disabled";
0182 };
0183
0184 bscc: i2c@406300 {
0185 clock-frequency = <390000>;
0186 compatible = "brcm,brcmstb-i2c";
0187 interrupt-parent = <&upg_irq0_intc>;
0188 reg = <0x406300 0x58>;
0189 interrupts = <26>;
0190 interrupt-names = "upg_bscc";
0191 status = "disabled";
0192 };
0193
0194 bscd: i2c@408980 {
0195 clock-frequency = <390000>;
0196 compatible = "brcm,brcmstb-i2c";
0197 interrupt-parent = <&upg_aon_irq0_intc>;
0198 reg = <0x408980 0x58>;
0199 interrupts = <27>;
0200 interrupt-names = "upg_bscd";
0201 status = "disabled";
0202 };
0203
0204 pwma: pwm@406400 {
0205 compatible = "brcm,bcm7038-pwm";
0206 reg = <0x406400 0x28>;
0207 #pwm-cells = <2>;
0208 clocks = <&upg_clk>;
0209 status = "disabled";
0210 };
0211
0212 pwmb: pwm@406700 {
0213 compatible = "brcm,bcm7038-pwm";
0214 reg = <0x406700 0x28>;
0215 #pwm-cells = <2>;
0216 clocks = <&upg_clk>;
0217 status = "disabled";
0218 };
0219
0220 watchdog: watchdog@4066a8 {
0221 clocks = <&upg_clk>;
0222 compatible = "brcm,bcm7038-wdt";
0223 reg = <0x4066a8 0x14>;
0224 status = "disabled";
0225 };
0226
0227 aon_pm_l2_intc: interrupt-controller@408240 {
0228 compatible = "brcm,l2-intc";
0229 reg = <0x408240 0x30>;
0230 interrupt-controller;
0231 #interrupt-cells = <1>;
0232 interrupt-parent = <&periph_intc>;
0233 interrupts = <50>;
0234 brcm,irq-can-wake;
0235 };
0236
0237 upg_gio: gpio@406500 {
0238 compatible = "brcm,brcmstb-gpio";
0239 reg = <0x406500 0xa0>;
0240 #gpio-cells = <2>;
0241 #interrupt-cells = <2>;
0242 gpio-controller;
0243 interrupt-controller;
0244 interrupt-parent = <&upg_irq0_intc>;
0245 interrupts = <6>;
0246 brcm,gpio-bank-widths = <32 32 32 29 4>;
0247 };
0248
0249 upg_gio_aon: gpio@408c00 {
0250 compatible = "brcm,brcmstb-gpio";
0251 reg = <0x408c00 0x60>;
0252 #gpio-cells = <2>;
0253 #interrupt-cells = <2>;
0254 gpio-controller;
0255 interrupt-controller;
0256 interrupt-parent = <&upg_aon_irq0_intc>;
0257 interrupts = <6>;
0258 interrupts-extended = <&upg_aon_irq0_intc 6>,
0259 <&aon_pm_l2_intc 5>;
0260 wakeup-source;
0261 brcm,gpio-bank-widths = <21 32 2>;
0262 };
0263
0264 enet0: ethernet@430000 {
0265 phy-mode = "internal";
0266 phy-handle = <&phy1>;
0267 mac-address = [ 00 10 18 36 23 1a ];
0268 compatible = "brcm,genet-v2";
0269 #address-cells = <0x1>;
0270 #size-cells = <0x1>;
0271 reg = <0x430000 0x4c8c>;
0272 interrupts = <24>, <25>;
0273 interrupt-parent = <&periph_intc>;
0274 status = "disabled";
0275
0276 mdio@e14 {
0277 compatible = "brcm,genet-mdio-v2";
0278 #address-cells = <0x1>;
0279 #size-cells = <0x0>;
0280 reg = <0xe14 0x8>;
0281
0282 phy1: ethernet-phy@1 {
0283 max-speed = <100>;
0284 reg = <0x1>;
0285 compatible = "brcm,40nm-ephy",
0286 "ethernet-phy-ieee802.3-c22";
0287 };
0288 };
0289 };
0290
0291 ehci0: usb@480300 {
0292 compatible = "brcm,bcm7358-ehci", "generic-ehci";
0293 reg = <0x480300 0x100>;
0294 native-endian;
0295 interrupt-parent = <&periph_intc>;
0296 interrupts = <65>;
0297 status = "disabled";
0298 };
0299
0300 ohci0: usb@480400 {
0301 compatible = "brcm,bcm7358-ohci", "generic-ohci";
0302 reg = <0x480400 0x100>;
0303 native-endian;
0304 no-big-frame-no;
0305 interrupt-parent = <&periph_intc>;
0306 interrupts = <66>;
0307 status = "disabled";
0308 };
0309
0310 hif_l2_intc: interrupt-controller@411000 {
0311 compatible = "brcm,l2-intc";
0312 reg = <0x411000 0x30>;
0313 interrupt-controller;
0314 #interrupt-cells = <1>;
0315 interrupt-parent = <&periph_intc>;
0316 interrupts = <30>;
0317 };
0318
0319 nand: nand@412800 {
0320 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
0321 #address-cells = <1>;
0322 #size-cells = <0>;
0323 reg-names = "nand";
0324 reg = <0x412800 0x400>;
0325 interrupt-parent = <&hif_l2_intc>;
0326 interrupts = <24>;
0327 status = "disabled";
0328 };
0329
0330 spi_l2_intc: interrupt-controller@411d00 {
0331 compatible = "brcm,l2-intc";
0332 reg = <0x411d00 0x30>;
0333 interrupt-controller;
0334 #interrupt-cells = <1>;
0335 interrupt-parent = <&periph_intc>;
0336 interrupts = <31>;
0337 };
0338
0339 qspi: spi@413000 {
0340 #address-cells = <0x1>;
0341 #size-cells = <0x0>;
0342 compatible = "brcm,spi-bcm-qspi",
0343 "brcm,spi-brcmstb-qspi";
0344 clocks = <&upg_clk>;
0345 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
0346 reg-names = "cs_reg", "hif_mspi", "bspi";
0347 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0348 interrupt-parent = <&spi_l2_intc>;
0349 interrupt-names = "spi_lr_fullness_reached",
0350 "spi_lr_session_aborted",
0351 "spi_lr_impatient",
0352 "spi_lr_session_done",
0353 "spi_lr_overread",
0354 "mspi_done",
0355 "mspi_halted";
0356 status = "disabled";
0357 };
0358
0359 mspi: spi@408a00 {
0360 #address-cells = <1>;
0361 #size-cells = <0>;
0362 compatible = "brcm,spi-bcm-qspi",
0363 "brcm,spi-brcmstb-mspi";
0364 clocks = <&upg_clk>;
0365 reg = <0x408a00 0x180>;
0366 reg-names = "mspi";
0367 interrupts = <0x14>;
0368 interrupt-parent = <&upg_aon_irq0_intc>;
0369 interrupt-names = "mspi_done";
0370 status = "disabled";
0371 };
0372
0373 waketimer: waketimer@408e80 {
0374 compatible = "brcm,brcmstb-waketimer";
0375 reg = <0x408e80 0x14>;
0376 interrupts = <0x3>;
0377 interrupt-parent = <&aon_pm_l2_intc>;
0378 interrupt-names = "timer";
0379 clocks = <&upg_clk>;
0380 status = "disabled";
0381 };
0382 };
0383 };
