0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7346";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <163125000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips5000";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018
0019 cpu@1 {
0020 compatible = "brcm,bmips5000";
0021 device_type = "cpu";
0022 reg = <1>;
0023 };
0024 };
0025
0026 aliases {
0027 uart0 = &uart0;
0028 };
0029
0030 cpu_intc: interrupt-controller {
0031 #address-cells = <0>;
0032 compatible = "mti,cpu-interrupt-controller";
0033
0034 interrupt-controller;
0035 #interrupt-cells = <1>;
0036 };
0037
0038 clocks {
0039 uart_clk: uart_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <81000000>;
0043 };
0044
0045 upg_clk: upg_clk {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <27000000>;
0049 };
0050 };
0051
0052 rdb {
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 compatible = "simple-bus";
0057 ranges = <0 0x10000000 0x01000000>;
0058
0059 periph_intc: interrupt-controller@411400 {
0060 compatible = "brcm,bcm7038-l1-intc";
0061 reg = <0x411400 0x30>, <0x411600 0x30>;
0062
0063 interrupt-controller;
0064 #interrupt-cells = <1>;
0065
0066 interrupt-parent = <&cpu_intc>;
0067 interrupts = <2>, <3>;
0068 };
0069
0070 sun_l2_intc: interrupt-controller@403000 {
0071 compatible = "brcm,l2-intc";
0072 reg = <0x403000 0x30>;
0073 interrupt-controller;
0074 #interrupt-cells = <1>;
0075 interrupt-parent = <&periph_intc>;
0076 interrupts = <51>;
0077 };
0078
0079 gisb-arb@400000 {
0080 compatible = "brcm,bcm7400-gisb-arb";
0081 reg = <0x400000 0xdc>;
0082 native-endian;
0083 interrupt-parent = <&sun_l2_intc>;
0084 interrupts = <0>, <2>;
0085 brcm,gisb-arb-master-mask = <0x673>;
0086 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
0087 "rdc_0", "raaga_0",
0088 "jtag_0", "svd_0";
0089 };
0090
0091 upg_irq0_intc: interrupt-controller@406780 {
0092 compatible = "brcm,bcm7120-l2-intc";
0093 reg = <0x406780 0x8>;
0094
0095 brcm,int-map-mask = <0x44>, <0xf000000>;
0096 brcm,int-fwd-mask = <0x70000>;
0097
0098 interrupt-controller;
0099 #interrupt-cells = <1>;
0100
0101 interrupt-parent = <&periph_intc>;
0102 interrupts = <59>, <57>;
0103 interrupt-names = "upg_main", "upg_bsc";
0104 };
0105
0106 upg_aon_irq0_intc: interrupt-controller@408b80 {
0107 compatible = "brcm,bcm7120-l2-intc";
0108 reg = <0x408b80 0x8>;
0109
0110 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
0111 brcm,int-fwd-mask = <0>;
0112 brcm,irq-can-wake;
0113
0114 interrupt-controller;
0115 #interrupt-cells = <1>;
0116
0117 interrupt-parent = <&periph_intc>;
0118 interrupts = <60>, <58>, <62>;
0119 interrupt-names = "upg_main_aon", "upg_bsc_aon",
0120 "upg_spi";
0121 };
0122
0123 sun_top_ctrl: syscon@404000 {
0124 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
0125 reg = <0x404000 0x51c>;
0126 native-endian;
0127 };
0128
0129 reboot {
0130 compatible = "brcm,brcmstb-reboot";
0131 syscon = <&sun_top_ctrl 0x304 0x308>;
0132 };
0133
0134 uart0: serial@406900 {
0135 compatible = "ns16550a";
0136 reg = <0x406900 0x20>;
0137 reg-io-width = <0x4>;
0138 reg-shift = <0x2>;
0139 native-endian;
0140 interrupt-parent = <&periph_intc>;
0141 interrupts = <64>;
0142 clocks = <&uart_clk>;
0143 status = "disabled";
0144 };
0145
0146 uart1: serial@406940 {
0147 compatible = "ns16550a";
0148 reg = <0x406940 0x20>;
0149 reg-io-width = <0x4>;
0150 reg-shift = <0x2>;
0151 native-endian;
0152 interrupt-parent = <&periph_intc>;
0153 interrupts = <65>;
0154 clocks = <&uart_clk>;
0155 status = "disabled";
0156 };
0157
0158 uart2: serial@406980 {
0159 compatible = "ns16550a";
0160 reg = <0x406980 0x20>;
0161 reg-io-width = <0x4>;
0162 reg-shift = <0x2>;
0163 native-endian;
0164 interrupt-parent = <&periph_intc>;
0165 interrupts = <66>;
0166 clocks = <&uart_clk>;
0167 status = "disabled";
0168 };
0169
0170 bsca: i2c@406200 {
0171 clock-frequency = <390000>;
0172 compatible = "brcm,brcmstb-i2c";
0173 interrupt-parent = <&upg_irq0_intc>;
0174 reg = <0x406200 0x58>;
0175 interrupts = <24>;
0176 interrupt-names = "upg_bsca";
0177 status = "disabled";
0178 };
0179
0180 bscb: i2c@406280 {
0181 clock-frequency = <390000>;
0182 compatible = "brcm,brcmstb-i2c";
0183 interrupt-parent = <&upg_irq0_intc>;
0184 reg = <0x406280 0x58>;
0185 interrupts = <25>;
0186 interrupt-names = "upg_bscb";
0187 status = "disabled";
0188 };
0189
0190 bscc: i2c@406300 {
0191 clock-frequency = <390000>;
0192 compatible = "brcm,brcmstb-i2c";
0193 interrupt-parent = <&upg_irq0_intc>;
0194 reg = <0x406300 0x58>;
0195 interrupts = <26>;
0196 interrupt-names = "upg_bscc";
0197 status = "disabled";
0198 };
0199
0200 bscd: i2c@406380 {
0201 clock-frequency = <390000>;
0202 compatible = "brcm,brcmstb-i2c";
0203 interrupt-parent = <&upg_irq0_intc>;
0204 reg = <0x406380 0x58>;
0205 interrupts = <27>;
0206 interrupt-names = "upg_bscd";
0207 status = "disabled";
0208 };
0209
0210 bsce: i2c@408980 {
0211 clock-frequency = <390000>;
0212 compatible = "brcm,brcmstb-i2c";
0213 interrupt-parent = <&upg_aon_irq0_intc>;
0214 reg = <0x408980 0x58>;
0215 interrupts = <27>;
0216 interrupt-names = "upg_bsce";
0217 status = "disabled";
0218 };
0219
0220 pwma: pwm@406580 {
0221 compatible = "brcm,bcm7038-pwm";
0222 reg = <0x406580 0x28>;
0223 #pwm-cells = <2>;
0224 clocks = <&upg_clk>;
0225 status = "disabled";
0226 };
0227
0228 pwmb: pwm@406800 {
0229 compatible = "brcm,bcm7038-pwm";
0230 reg = <0x406800 0x28>;
0231 #pwm-cells = <2>;
0232 clocks = <&upg_clk>;
0233 status = "disabled";
0234 };
0235
0236 watchdog: watchdog@4067e8 {
0237 clocks = <&upg_clk>;
0238 compatible = "brcm,bcm7038-wdt";
0239 reg = <0x4067e8 0x14>;
0240 status = "disabled";
0241 };
0242
0243 aon_pm_l2_intc: interrupt-controller@408440 {
0244 compatible = "brcm,l2-intc";
0245 reg = <0x408440 0x30>;
0246 interrupt-controller;
0247 #interrupt-cells = <1>;
0248 interrupt-parent = <&periph_intc>;
0249 interrupts = <53>;
0250 brcm,irq-can-wake;
0251 };
0252
0253 aon_ctrl: syscon@408000 {
0254 compatible = "brcm,brcmstb-aon-ctrl";
0255 reg = <0x408000 0x100>, <0x408200 0x200>;
0256 reg-names = "aon-ctrl", "aon-sram";
0257 };
0258
0259 timers: timer@4067c0 {
0260 compatible = "brcm,brcmstb-timers";
0261 reg = <0x4067c0 0x40>;
0262 };
0263
0264 upg_gio: gpio@406700 {
0265 compatible = "brcm,brcmstb-gpio";
0266 reg = <0x406700 0x60>;
0267 #gpio-cells = <2>;
0268 #interrupt-cells = <2>;
0269 gpio-controller;
0270 interrupt-controller;
0271 interrupt-parent = <&upg_irq0_intc>;
0272 interrupts = <6>;
0273 brcm,gpio-bank-widths = <32 32 16>;
0274 };
0275
0276 upg_gio_aon: gpio@408c00 {
0277 compatible = "brcm,brcmstb-gpio";
0278 reg = <0x408c00 0x60>;
0279 #gpio-cells = <2>;
0280 #interrupt-cells = <2>;
0281 gpio-controller;
0282 interrupt-controller;
0283 interrupt-parent = <&upg_aon_irq0_intc>;
0284 interrupts = <6>;
0285 interrupts-extended = <&upg_aon_irq0_intc 6>,
0286 <&aon_pm_l2_intc 5>;
0287 wakeup-source;
0288 brcm,gpio-bank-widths = <27 32 2>;
0289 };
0290
0291 enet0: ethernet@430000 {
0292 phy-mode = "internal";
0293 phy-handle = <&phy1>;
0294 mac-address = [ 00 10 18 36 23 1a ];
0295 compatible = "brcm,genet-v2";
0296 #address-cells = <0x1>;
0297 #size-cells = <0x1>;
0298 reg = <0x430000 0x4c8c>;
0299 interrupts = <24>, <25>;
0300 interrupt-parent = <&periph_intc>;
0301 status = "disabled";
0302
0303 mdio@e14 {
0304 compatible = "brcm,genet-mdio-v2";
0305 #address-cells = <0x1>;
0306 #size-cells = <0x0>;
0307 reg = <0xe14 0x8>;
0308
0309 phy1: ethernet-phy@1 {
0310 max-speed = <100>;
0311 reg = <0x1>;
0312 compatible = "brcm,40nm-ephy",
0313 "ethernet-phy-ieee802.3-c22";
0314 };
0315 };
0316 };
0317
0318 ehci0: usb@480300 {
0319 compatible = "brcm,bcm7346-ehci", "generic-ehci";
0320 reg = <0x480300 0x100>;
0321 native-endian;
0322 interrupt-parent = <&periph_intc>;
0323 interrupts = <68>;
0324 status = "disabled";
0325 };
0326
0327 ohci0: usb@480400 {
0328 compatible = "brcm,bcm7346-ohci", "generic-ohci";
0329 reg = <0x480400 0x100>;
0330 native-endian;
0331 no-big-frame-no;
0332 interrupt-parent = <&periph_intc>;
0333 interrupts = <70>;
0334 status = "disabled";
0335 };
0336
0337 ehci1: usb@480500 {
0338 compatible = "brcm,bcm7346-ehci", "generic-ehci";
0339 reg = <0x480500 0x100>;
0340 native-endian;
0341 interrupt-parent = <&periph_intc>;
0342 interrupts = <69>;
0343 status = "disabled";
0344 };
0345
0346 ohci1: usb@480600 {
0347 compatible = "brcm,bcm7346-ohci", "generic-ohci";
0348 reg = <0x480600 0x100>;
0349 native-endian;
0350 no-big-frame-no;
0351 interrupt-parent = <&periph_intc>;
0352 interrupts = <71>;
0353 status = "disabled";
0354 };
0355
0356 ehci2: usb@490300 {
0357 compatible = "brcm,bcm7346-ehci", "generic-ehci";
0358 reg = <0x490300 0x100>;
0359 native-endian;
0360 interrupt-parent = <&periph_intc>;
0361 interrupts = <73>;
0362 status = "disabled";
0363 };
0364
0365 ohci2: usb@490400 {
0366 compatible = "brcm,bcm7346-ohci", "generic-ohci";
0367 reg = <0x490400 0x100>;
0368 native-endian;
0369 no-big-frame-no;
0370 interrupt-parent = <&periph_intc>;
0371 interrupts = <75>;
0372 status = "disabled";
0373 };
0374
0375 ehci3: usb@490500 {
0376 compatible = "brcm,bcm7346-ehci", "generic-ehci";
0377 reg = <0x490500 0x100>;
0378 native-endian;
0379 interrupt-parent = <&periph_intc>;
0380 interrupts = <74>;
0381 status = "disabled";
0382 };
0383
0384 ohci3: usb@490600 {
0385 compatible = "brcm,bcm7346-ohci", "generic-ohci";
0386 reg = <0x490600 0x100>;
0387 native-endian;
0388 no-big-frame-no;
0389 interrupt-parent = <&periph_intc>;
0390 interrupts = <76>;
0391 status = "disabled";
0392 };
0393
0394 hif_l2_intc: interrupt-controller@411000 {
0395 compatible = "brcm,l2-intc";
0396 reg = <0x411000 0x30>;
0397 interrupt-controller;
0398 #interrupt-cells = <1>;
0399 interrupt-parent = <&periph_intc>;
0400 interrupts = <30>;
0401 };
0402
0403 nand: nand@412800 {
0404 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407 reg-names = "nand";
0408 reg = <0x412800 0x400>;
0409 interrupt-parent = <&hif_l2_intc>;
0410 interrupts = <24>;
0411 status = "disabled";
0412 };
0413
0414 sata: sata@181000 {
0415 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
0416 reg-names = "ahci", "top-ctrl";
0417 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
0418 interrupt-parent = <&periph_intc>;
0419 interrupts = <40>;
0420 #address-cells = <1>;
0421 #size-cells = <0>;
0422 status = "disabled";
0423
0424 sata0: sata-port@0 {
0425 reg = <0>;
0426 phys = <&sata_phy0>;
0427 };
0428
0429 sata1: sata-port@1 {
0430 reg = <1>;
0431 phys = <&sata_phy1>;
0432 };
0433 };
0434
0435 sata_phy: sata-phy@180100 {
0436 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
0437 reg = <0x180100 0x0eff>;
0438 reg-names = "phy";
0439 #address-cells = <1>;
0440 #size-cells = <0>;
0441 status = "disabled";
0442
0443 sata_phy0: sata-phy@0 {
0444 reg = <0>;
0445 #phy-cells = <0>;
0446 };
0447
0448 sata_phy1: sata-phy@1 {
0449 reg = <1>;
0450 #phy-cells = <0>;
0451 };
0452 };
0453
0454 sdhci0: sdhci@413500 {
0455 compatible = "brcm,bcm7425-sdhci";
0456 reg = <0x413500 0x100>;
0457 interrupt-parent = <&periph_intc>;
0458 interrupts = <85>;
0459 status = "disabled";
0460 };
0461
0462 spi_l2_intc: interrupt-controller@411d00 {
0463 compatible = "brcm,l2-intc";
0464 reg = <0x411d00 0x30>;
0465 interrupt-controller;
0466 #interrupt-cells = <1>;
0467 interrupt-parent = <&periph_intc>;
0468 interrupts = <31>;
0469 };
0470
0471 qspi: spi@413000 {
0472 #address-cells = <0x1>;
0473 #size-cells = <0x0>;
0474 compatible = "brcm,spi-bcm-qspi",
0475 "brcm,spi-brcmstb-qspi";
0476 clocks = <&upg_clk>;
0477 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
0478 reg-names = "cs_reg", "hif_mspi", "bspi";
0479 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0480 interrupt-parent = <&spi_l2_intc>;
0481 interrupt-names = "spi_lr_fullness_reached",
0482 "spi_lr_session_aborted",
0483 "spi_lr_impatient",
0484 "spi_lr_session_done",
0485 "spi_lr_overread",
0486 "mspi_done",
0487 "mspi_halted";
0488 status = "disabled";
0489 };
0490
0491 mspi: spi@408a00 {
0492 #address-cells = <1>;
0493 #size-cells = <0>;
0494 compatible = "brcm,spi-bcm-qspi",
0495 "brcm,spi-brcmstb-mspi";
0496 clocks = <&upg_clk>;
0497 reg = <0x408a00 0x180>;
0498 reg-names = "mspi";
0499 interrupts = <0x14>;
0500 interrupt-parent = <&upg_aon_irq0_intc>;
0501 interrupt-names = "mspi_done";
0502 status = "disabled";
0503 };
0504
0505 waketimer: waketimer@408e80 {
0506 compatible = "brcm,brcmstb-waketimer";
0507 reg = <0x408e80 0x14>;
0508 interrupts = <0x3>;
0509 interrupt-parent = <&aon_pm_l2_intc>;
0510 interrupt-names = "timer";
0511 clocks = <&upg_clk>;
0512 status = "disabled";
0513 };
0514 };
0515
0516 memory_controllers {
0517 compatible = "simple-bus";
0518 ranges = <0x0 0x103b0000 0xa000>;
0519 #address-cells = <1>;
0520 #size-cells = <1>;
0521
0522 memory-controller@0 {
0523 compatible = "brcm,brcmstb-memc", "simple-bus";
0524 ranges = <0x0 0x0 0xa000>;
0525 #address-cells = <1>;
0526 #size-cells = <1>;
0527
0528 memc-arb@1000 {
0529 compatible = "brcm,brcmstb-memc-arb";
0530 reg = <0x1000 0x248>;
0531 };
0532
0533 memc-ddr@2000 {
0534 compatible = "brcm,brcmstb-memc-ddr";
0535 reg = <0x2000 0x300>;
0536 };
0537
0538 ddr-phy@6000 {
0539 compatible = "brcm,brcmstb-ddr-phy";
0540 reg = <0x6000 0xc8>;
0541 };
0542
0543 shimphy@8000 {
0544 compatible = "brcm,brcmstb-ddr-shimphy";
0545 reg = <0x8000 0x13c>;
0546 };
0547 };
0548 };
0549 };
