0001 // SPDX-License-Identifier: GPL-2.0
0002 / {
0003 #address-cells = <1>;
0004 #size-cells = <1>;
0005 compatible = "brcm,bcm7125";
0006
0007 cpus {
0008 #address-cells = <1>;
0009 #size-cells = <0>;
0010
0011 mips-hpt-frequency = <202500000>;
0012
0013 cpu@0 {
0014 compatible = "brcm,bmips4380";
0015 device_type = "cpu";
0016 reg = <0>;
0017 };
0018
0019 cpu@1 {
0020 compatible = "brcm,bmips4380";
0021 device_type = "cpu";
0022 reg = <1>;
0023 };
0024 };
0025
0026 aliases {
0027 uart0 = &uart0;
0028 };
0029
0030 cpu_intc: interrupt-controller {
0031 #address-cells = <0>;
0032 compatible = "mti,cpu-interrupt-controller";
0033
0034 interrupt-controller;
0035 #interrupt-cells = <1>;
0036 };
0037
0038 clocks {
0039 uart_clk: uart_clk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <81000000>;
0043 };
0044
0045 upg_clk: upg_clk {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <27000000>;
0049 };
0050 };
0051
0052 rdb {
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 compatible = "simple-bus";
0057 ranges = <0 0x10000000 0x01000000>;
0058
0059 periph_intc: interrupt-controller@441400 {
0060 compatible = "brcm,bcm7038-l1-intc";
0061 reg = <0x441400 0x30>, <0x441600 0x30>;
0062
0063 interrupt-controller;
0064 #interrupt-cells = <1>;
0065
0066 interrupt-parent = <&cpu_intc>;
0067 interrupts = <2>, <3>;
0068 };
0069
0070 sun_l2_intc: interrupt-controller@401800 {
0071 compatible = "brcm,l2-intc";
0072 reg = <0x401800 0x30>;
0073 interrupt-controller;
0074 #interrupt-cells = <1>;
0075 interrupt-parent = <&periph_intc>;
0076 interrupts = <23>;
0077 };
0078
0079 gisb-arb@400000 {
0080 compatible = "brcm,bcm7400-gisb-arb";
0081 reg = <0x400000 0xdc>;
0082 native-endian;
0083 interrupt-parent = <&sun_l2_intc>;
0084 interrupts = <0>, <2>;
0085 brcm,gisb-arb-master-mask = <0x2f7>;
0086 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
0087 "bsp_0", "rdc_0", "rptd_0",
0088 "avd_0", "jtag_0";
0089 };
0090
0091 upg_irq0_intc: interrupt-controller@406780 {
0092 compatible = "brcm,bcm7120-l2-intc";
0093 reg = <0x406780 0x8>;
0094
0095 brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
0096 brcm,int-fwd-mask = <0x70000>;
0097
0098 interrupt-controller;
0099 #interrupt-cells = <1>;
0100
0101 interrupt-parent = <&periph_intc>;
0102 interrupts = <18>, <19>, <20>;
0103 interrupt-names = "upg_main", "upg_bsc", "upg_spi";
0104 };
0105
0106 sun_top_ctrl: syscon@404000 {
0107 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
0108 reg = <0x404000 0x60c>;
0109 native-endian;
0110 };
0111
0112 reboot {
0113 compatible = "brcm,bcm7038-reboot";
0114 syscon = <&sun_top_ctrl 0x8 0x14>;
0115 };
0116
0117 uart0: serial@406b00 {
0118 compatible = "ns16550a";
0119 reg = <0x406b00 0x20>;
0120 reg-io-width = <0x4>;
0121 reg-shift = <0x2>;
0122 native-endian;
0123 interrupt-parent = <&periph_intc>;
0124 interrupts = <21>;
0125 clocks = <&uart_clk>;
0126 status = "disabled";
0127 };
0128
0129 uart1: serial@406b40 {
0130 compatible = "ns16550a";
0131 reg = <0x406b40 0x20>;
0132 reg-io-width = <0x4>;
0133 reg-shift = <0x2>;
0134 native-endian;
0135 interrupt-parent = <&periph_intc>;
0136 interrupts = <64>;
0137 clocks = <&uart_clk>;
0138 status = "disabled";
0139 };
0140
0141 uart2: serial@406b80 {
0142 compatible = "ns16550a";
0143 reg = <0x406b80 0x20>;
0144 reg-io-width = <0x4>;
0145 reg-shift = <0x2>;
0146 native-endian;
0147 interrupt-parent = <&periph_intc>;
0148 interrupts = <65>;
0149 clocks = <&uart_clk>;
0150 status = "disabled";
0151 };
0152
0153 bsca: i2c@406200 {
0154 clock-frequency = <390000>;
0155 compatible = "brcm,brcmstb-i2c";
0156 interrupt-parent = <&upg_irq0_intc>;
0157 reg = <0x406200 0x58>;
0158 interrupts = <24>;
0159 interrupt-names = "upg_bsca";
0160 status = "disabled";
0161 };
0162
0163 bscb: i2c@406280 {
0164 clock-frequency = <390000>;
0165 compatible = "brcm,brcmstb-i2c";
0166 interrupt-parent = <&upg_irq0_intc>;
0167 reg = <0x406280 0x58>;
0168 interrupts = <25>;
0169 interrupt-names = "upg_bscb";
0170 status = "disabled";
0171 };
0172
0173 bscc: i2c@406300 {
0174 clock-frequency = <390000>;
0175 compatible = "brcm,brcmstb-i2c";
0176 interrupt-parent = <&upg_irq0_intc>;
0177 reg = <0x406300 0x58>;
0178 interrupts = <26>;
0179 interrupt-names = "upg_bscc";
0180 status = "disabled";
0181 };
0182
0183 bscd: i2c@406380 {
0184 clock-frequency = <390000>;
0185 compatible = "brcm,brcmstb-i2c";
0186 interrupt-parent = <&upg_irq0_intc>;
0187 reg = <0x406380 0x58>;
0188 interrupts = <27>;
0189 interrupt-names = "upg_bscd";
0190 status = "disabled";
0191 };
0192
0193 pwma: pwm@406580 {
0194 compatible = "brcm,bcm7038-pwm";
0195 reg = <0x406580 0x28>;
0196 #pwm-cells = <2>;
0197 clocks = <&upg_clk>;
0198 status = "disabled";
0199 };
0200
0201 watchdog: watchdog@4067e8 {
0202 clocks = <&upg_clk>;
0203 compatible = "brcm,bcm7038-wdt";
0204 reg = <0x4067e8 0x14>;
0205 status = "disabled";
0206 };
0207
0208 upg_gio: gpio@406700 {
0209 compatible = "brcm,brcmstb-gpio";
0210 reg = <0x406700 0x80>;
0211 #gpio-cells = <2>;
0212 #interrupt-cells = <2>;
0213 gpio-controller;
0214 interrupt-controller;
0215 interrupt-parent = <&upg_irq0_intc>;
0216 interrupts = <6>;
0217 brcm,gpio-bank-widths = <32 32 32 18>;
0218 };
0219
0220 ehci0: usb@488300 {
0221 compatible = "brcm,bcm7125-ehci", "generic-ehci";
0222 reg = <0x488300 0x100>;
0223 native-endian;
0224 interrupt-parent = <&periph_intc>;
0225 interrupts = <60>;
0226 status = "disabled";
0227 };
0228
0229 ohci0: usb@488400 {
0230 compatible = "brcm,bcm7125-ohci", "generic-ohci";
0231 reg = <0x488400 0x100>;
0232 native-endian;
0233 interrupt-parent = <&periph_intc>;
0234 interrupts = <61>;
0235 status = "disabled";
0236 };
0237
0238 spi_l2_intc: interrupt-controller@411d00 {
0239 compatible = "brcm,l2-intc";
0240 reg = <0x411d00 0x30>;
0241 interrupt-controller;
0242 #interrupt-cells = <1>;
0243 interrupt-parent = <&periph_intc>;
0244 interrupts = <79>;
0245 };
0246
0247 qspi: spi@443000 {
0248 #address-cells = <0x1>;
0249 #size-cells = <0x0>;
0250 compatible = "brcm,spi-bcm-qspi",
0251 "brcm,spi-brcmstb-qspi";
0252 clocks = <&upg_clk>;
0253 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
0254 reg-names = "cs_reg", "hif_mspi", "bspi";
0255 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
0256 interrupt-parent = <&spi_l2_intc>;
0257 interrupt-names = "spi_lr_fullness_reached",
0258 "spi_lr_session_aborted",
0259 "spi_lr_impatient",
0260 "spi_lr_session_done",
0261 "spi_lr_overread",
0262 "mspi_done",
0263 "mspi_halted";
0264 status = "disabled";
0265 };
0266
0267 mspi: spi@406400 {
0268 #address-cells = <1>;
0269 #size-cells = <0>;
0270 compatible = "brcm,spi-bcm-qspi",
0271 "brcm,spi-brcmstb-mspi";
0272 clocks = <&upg_clk>;
0273 reg = <0x406400 0x180>;
0274 reg-names = "mspi";
0275 interrupts = <0x14>;
0276 interrupt-parent = <&upg_irq0_intc>;
0277 interrupt-names = "mspi_done";
0278 status = "disabled";
0279 };
0280 };
0281 };
