0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 #include "dt-bindings/clock/bcm6368-clock.h"
0004 #include "dt-bindings/reset/bcm6368-reset.h"
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 compatible = "brcm,bcm6368";
0010
0011 cpus {
0012 #address-cells = <1>;
0013 #size-cells = <0>;
0014
0015 mips-hpt-frequency = <200000000>;
0016
0017 cpu@0 {
0018 compatible = "brcm,bmips4350";
0019 device_type = "cpu";
0020 reg = <0>;
0021 };
0022
0023 cpu@1 {
0024 compatible = "brcm,bmips4350";
0025 device_type = "cpu";
0026 reg = <1>;
0027 };
0028 };
0029
0030 clocks {
0031 periph_osc: periph-osc {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <50000000>;
0035 clock-output-names = "periph";
0036 };
0037 };
0038
0039 aliases {
0040 nflash = &nflash;
0041 pflash = &pflash;
0042 serial0 = &uart0;
0043 serial1 = &uart1;
0044 spi0 = &lsspi;
0045 };
0046
0047 cpu_intc: interrupt-controller {
0048 #address-cells = <0>;
0049 compatible = "mti,cpu-interrupt-controller";
0050
0051 interrupt-controller;
0052 #interrupt-cells = <1>;
0053 };
0054
0055 ubus {
0056 #address-cells = <1>;
0057 #size-cells = <1>;
0058
0059 compatible = "simple-bus";
0060 ranges;
0061
0062 periph_clk: clock-controller@10000004 {
0063 compatible = "brcm,bcm6368-clocks";
0064 reg = <0x10000004 0x4>;
0065 #clock-cells = <1>;
0066 };
0067
0068 pll_cntl: syscon@100000008 {
0069 compatible = "syscon";
0070 reg = <0x10000008 0x4>;
0071 native-endian;
0072
0073 reboot {
0074 compatible = "syscon-reboot";
0075 offset = <0x0>;
0076 mask = <0x1>;
0077 };
0078 };
0079
0080 periph_rst: reset-controller@10000010 {
0081 compatible = "brcm,bcm6345-reset";
0082 reg = <0x10000010 0x4>;
0083 #reset-cells = <1>;
0084 };
0085
0086 periph_intc: interrupt-controller@10000020 {
0087 compatible = "brcm,bcm6345-l1-intc";
0088 reg = <0x10000020 0x10>,
0089 <0x10000030 0x10>;
0090
0091 interrupt-controller;
0092 #interrupt-cells = <1>;
0093
0094 interrupt-parent = <&cpu_intc>;
0095 interrupts = <2>, <3>;
0096 };
0097
0098 wdt: watchdog@1000005c {
0099 compatible = "brcm,bcm7038-wdt";
0100 reg = <0x1000005c 0xc>;
0101
0102 clocks = <&periph_osc>;
0103 clock-names = "refclk";
0104
0105 timeout-sec = <30>;
0106 };
0107
0108 leds0: led-controller@100000d0 {
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111 compatible = "brcm,bcm6358-leds";
0112 reg = <0x100000d0 0x8>;
0113
0114 status = "disabled";
0115 };
0116
0117 uart0: serial@10000100 {
0118 compatible = "brcm,bcm6345-uart";
0119 reg = <0x10000100 0x18>;
0120
0121 interrupt-parent = <&periph_intc>;
0122 interrupts = <2>;
0123
0124 clocks = <&periph_osc>;
0125 clock-names = "refclk";
0126
0127 status = "disabled";
0128 };
0129
0130 uart1: serial@10000120 {
0131 compatible = "brcm,bcm6345-uart";
0132 reg = <0x10000120 0x18>;
0133
0134 interrupt-parent = <&periph_intc>;
0135 interrupts = <3>;
0136
0137 clocks = <&periph_osc>;
0138 clock-names = "refclk";
0139
0140 status = "disabled";
0141 };
0142
0143 nflash: nand@10000200 {
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146 compatible = "brcm,nand-bcm6368",
0147 "brcm,brcmnand-v2.1",
0148 "brcm,brcmnand";
0149 reg = <0x10000200 0x180>,
0150 <0x10000600 0x200>,
0151 <0x10000070 0x10>;
0152 reg-names = "nand",
0153 "nand-cache",
0154 "nand-int-base";
0155
0156 interrupt-parent = <&periph_intc>;
0157 interrupts = <10>;
0158
0159 clocks = <&periph_clk BCM6368_CLK_NAND>;
0160 clock-names = "nand";
0161
0162 status = "disabled";
0163 };
0164
0165 lsspi: spi@10000800 {
0166 #address-cells = <1>;
0167 #size-cells = <0>;
0168 compatible = "brcm,bcm6358-spi";
0169 reg = <0x10000800 0x70c>;
0170
0171 interrupt-parent = <&periph_intc>;
0172 interrupts = <1>;
0173
0174 clocks = <&periph_clk BCM6368_CLK_SPI>;
0175 clock-names = "spi";
0176
0177 resets = <&periph_rst BCM6368_RST_SPI>;
0178 reset-names = "spi";
0179
0180 status = "disabled";
0181 };
0182
0183 ehci: usb@10001500 {
0184 compatible = "brcm,bcm6368-ehci", "generic-ehci";
0185 reg = <0x10001500 0x100>;
0186 big-endian;
0187
0188 interrupt-parent = <&periph_intc>;
0189 interrupts = <7>;
0190
0191 phys = <&usbh 0>;
0192 phy-names = "usb";
0193
0194 status = "disabled";
0195 };
0196
0197 ohci: usb@10001600 {
0198 compatible = "brcm,bcm6368-ohci", "generic-ohci";
0199 reg = <0x10001600 0x100>;
0200 big-endian;
0201 no-big-frame-no;
0202
0203 interrupt-parent = <&periph_intc>;
0204 interrupts = <5>;
0205
0206 phys = <&usbh 0>;
0207 phy-names = "usb";
0208
0209 status = "disabled";
0210 };
0211
0212 usbh: usb-phy@10001700 {
0213 compatible = "brcm,bcm6368-usbh-phy";
0214 reg = <0x10001700 0x38>;
0215 #phy-cells = <1>;
0216
0217 clocks = <&periph_clk BCM6368_CLK_USBH>;
0218 clock-names = "usbh";
0219
0220 resets = <&periph_rst BCM6368_RST_USBH>;
0221 reset-names = "usbh";
0222
0223 status = "disabled";
0224 };
0225
0226 random: rng@10004180 {
0227 compatible = "brcm,bcm6368-rng";
0228 reg = <0x10004180 0x14>;
0229
0230 clocks = <&periph_clk BCM6368_CLK_IPSEC>;
0231 clock-names = "ipsec";
0232
0233 resets = <&periph_rst BCM6368_RST_IPSEC>;
0234 reset-names = "ipsec";
0235 };
0236 };
0237
0238 pflash: nor@18000000 {
0239 #address-cells = <1>;
0240 #size-cells = <1>;
0241 compatible = "cfi-flash";
0242 reg = <0x18000000 0x2000000>;
0243 bank-width = <2>;
0244
0245 status = "disabled";
0246 };
0247 };
