0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 #include "dt-bindings/clock/bcm6362-clock.h"
0004 #include "dt-bindings/reset/bcm6362-reset.h"
0005 #include "dt-bindings/soc/bcm6362-pm.h"
0006
0007 / {
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 compatible = "brcm,bcm6362";
0011
0012 cpus {
0013 #address-cells = <1>;
0014 #size-cells = <0>;
0015
0016 mips-hpt-frequency = <200000000>;
0017
0018 cpu@0 {
0019 compatible = "brcm,bmips4350";
0020 device_type = "cpu";
0021 reg = <0>;
0022 };
0023
0024 cpu@1 {
0025 compatible = "brcm,bmips4350";
0026 device_type = "cpu";
0027 reg = <1>;
0028 };
0029 };
0030
0031 clocks {
0032 periph_osc: periph-osc {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 clock-frequency = <50000000>;
0036 clock-output-names = "periph";
0037 };
0038
0039 hsspi_osc: hsspi-osc {
0040 compatible = "fixed-clock";
0041
0042 #clock-cells = <0>;
0043
0044 clock-frequency = <400000000>;
0045 clock-output-names = "hsspi_osc";
0046 };
0047 };
0048
0049 aliases {
0050 nflash = &nflash;
0051 serial0 = &uart0;
0052 serial1 = &uart1;
0053 spi0 = &lsspi;
0054 spi1 = &hsspi;
0055 };
0056
0057 cpu_intc: interrupt-controller {
0058 #address-cells = <0>;
0059 compatible = "mti,cpu-interrupt-controller";
0060
0061 interrupt-controller;
0062 #interrupt-cells = <1>;
0063 };
0064
0065 ubus {
0066 #address-cells = <1>;
0067 #size-cells = <1>;
0068
0069 compatible = "simple-bus";
0070 ranges;
0071
0072 periph_clk: clock-controller@10000004 {
0073 compatible = "brcm,bcm6362-clocks";
0074 reg = <0x10000004 0x4>;
0075 #clock-cells = <1>;
0076 };
0077
0078 pll_cntl: syscon@10000008 {
0079 compatible = "syscon";
0080 reg = <0x10000008 0x4>;
0081 native-endian;
0082
0083 reboot {
0084 compatible = "syscon-reboot";
0085 offset = <0x0>;
0086 mask = <0x1>;
0087 };
0088 };
0089
0090 periph_rst: reset-controller@10000010 {
0091 compatible = "brcm,bcm6345-reset";
0092 reg = <0x10000010 0x4>;
0093 #reset-cells = <1>;
0094 };
0095
0096 periph_intc: interrupt-controller@10000020 {
0097 compatible = "brcm,bcm6345-l1-intc";
0098 reg = <0x10000020 0x10>,
0099 <0x10000030 0x10>;
0100
0101 interrupt-controller;
0102 #interrupt-cells = <1>;
0103
0104 interrupt-parent = <&cpu_intc>;
0105 interrupts = <2>, <3>;
0106 };
0107
0108 wdt: watchdog@1000005c {
0109 compatible = "brcm,bcm7038-wdt";
0110 reg = <0x1000005c 0xc>;
0111
0112 clocks = <&periph_osc>;
0113 clock-names = "refclk";
0114
0115 timeout-sec = <30>;
0116 };
0117
0118 uart0: serial@10000100 {
0119 compatible = "brcm,bcm6345-uart";
0120 reg = <0x10000100 0x18>;
0121
0122 interrupt-parent = <&periph_intc>;
0123 interrupts = <3>;
0124
0125 clocks = <&periph_osc>;
0126 clock-names = "refclk";
0127
0128 status = "disabled";
0129 };
0130
0131 uart1: serial@10000120 {
0132 compatible = "brcm,bcm6345-uart";
0133 reg = <0x10000120 0x18>;
0134
0135 interrupt-parent = <&periph_intc>;
0136 interrupts = <4>;
0137
0138 clocks = <&periph_osc>;
0139 clock-names = "refclk";
0140
0141 status = "disabled";
0142 };
0143
0144 nflash: nand@10000200 {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 compatible = "brcm,nand-bcm6368",
0148 "brcm,brcmnand-v2.2",
0149 "brcm,brcmnand";
0150 reg = <0x10000200 0x180>,
0151 <0x10000600 0x200>,
0152 <0x10000070 0x10>;
0153 reg-names = "nand",
0154 "nand-cache",
0155 "nand-int-base";
0156
0157 interrupt-parent = <&periph_intc>;
0158 interrupts = <12>;
0159
0160 clocks = <&periph_clk BCM6362_CLK_NAND>;
0161 clock-names = "nand";
0162
0163 status = "disabled";
0164 };
0165
0166 lsspi: spi@10000800 {
0167 #address-cells = <1>;
0168 #size-cells = <0>;
0169 compatible = "brcm,bcm6358-spi";
0170 reg = <0x10000800 0x70c>;
0171
0172 interrupt-parent = <&periph_intc>;
0173 interrupts = <2>;
0174
0175 clocks = <&periph_clk BCM6362_CLK_SPI>;
0176 clock-names = "spi";
0177
0178 resets = <&periph_rst BCM6362_RST_SPI>;
0179 reset-names = "spi";
0180
0181 status = "disabled";
0182 };
0183
0184 hsspi: spi@10001000 {
0185 #address-cells = <1>;
0186 #size-cells = <0>;
0187 compatible = "brcm,bcm6328-hsspi";
0188 reg = <0x10001000 0x600>;
0189
0190 interrupt-parent = <&periph_intc>;
0191 interrupts = <5>;
0192
0193 clocks = <&periph_clk BCM6362_CLK_HSSPI>,
0194 <&hsspi_osc>;
0195 clock-names = "hsspi",
0196 "pll";
0197
0198 resets = <&periph_rst BCM6362_RST_SPI>;
0199 reset-names = "hsspi";
0200
0201 status = "disabled";
0202 };
0203
0204 periph_pwr: power-controller@10001848 {
0205 compatible = "brcm,bcm6362-power-controller";
0206 reg = <0x10001848 0x4>;
0207 #power-domain-cells = <1>;
0208 };
0209
0210 leds0: led-controller@10001900 {
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213 compatible = "brcm,bcm6328-leds";
0214 reg = <0x10001900 0x24>;
0215
0216 status = "disabled";
0217 };
0218
0219 ehci: usb@10002500 {
0220 compatible = "brcm,bcm6362-ehci", "generic-ehci";
0221 reg = <0x10002500 0x100>;
0222 big-endian;
0223
0224 interrupt-parent = <&periph_intc>;
0225 interrupts = <10>;
0226
0227 phys = <&usbh 0>;
0228 phy-names = "usb";
0229
0230 status = "disabled";
0231 };
0232
0233 ohci: usb@10002600 {
0234 compatible = "brcm,bcm6362-ohci", "generic-ohci";
0235 reg = <0x10002600 0x100>;
0236 big-endian;
0237 no-big-frame-no;
0238
0239 interrupt-parent = <&periph_intc>;
0240 interrupts = <9>;
0241
0242 phys = <&usbh 0>;
0243 phy-names = "usb";
0244
0245 status = "disabled";
0246 };
0247
0248 usbh: usb-phy@10002700 {
0249 compatible = "brcm,bcm6362-usbh-phy";
0250 reg = <0x10002700 0x38>;
0251
0252 #phy-cells = <1>;
0253
0254 clocks = <&periph_clk BCM6362_CLK_USBH>;
0255 clock-names = "usbh";
0256
0257 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
0258
0259 resets = <&periph_rst BCM6362_RST_USBH>;
0260 reset-names = "usbh";
0261
0262 status = "disabled";
0263 };
0264 };
0265 };
