0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 #include "dt-bindings/clock/bcm6358-clock.h"
0004 #include "dt-bindings/reset/bcm6358-reset.h"
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 compatible = "brcm,bcm6358";
0010
0011 cpus {
0012 #address-cells = <1>;
0013 #size-cells = <0>;
0014
0015 mips-hpt-frequency = <150000000>;
0016
0017 cpu@0 {
0018 compatible = "brcm,bmips4350";
0019 device_type = "cpu";
0020 reg = <0>;
0021 };
0022
0023 cpu@1 {
0024 compatible = "brcm,bmips4350";
0025 device_type = "cpu";
0026 reg = <1>;
0027 };
0028 };
0029
0030 clocks {
0031 periph_osc: periph-osc {
0032 compatible = "fixed-clock";
0033 #clock-cells = <0>;
0034 clock-frequency = <50000000>;
0035 clock-output-names = "periph";
0036 };
0037 };
0038
0039 aliases {
0040 pflash = &pflash;
0041 serial0 = &uart0;
0042 serial1 = &uart1;
0043 spi0 = &lsspi;
0044 };
0045
0046 cpu_intc: interrupt-controller {
0047 #address-cells = <0>;
0048 compatible = "mti,cpu-interrupt-controller";
0049
0050 interrupt-controller;
0051 #interrupt-cells = <1>;
0052 };
0053
0054 ubus {
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057
0058 compatible = "simple-bus";
0059 ranges;
0060
0061 periph_clk: clock-controller@fffe0004 {
0062 compatible = "brcm,bcm6358-clocks";
0063 reg = <0xfffe0004 0x4>;
0064 #clock-cells = <1>;
0065 };
0066
0067 pll_cntl: syscon@fffe0008 {
0068 compatible = "syscon";
0069 reg = <0xfffe0008 0x4>;
0070 native-endian;
0071
0072 reboot {
0073 compatible = "syscon-reboot";
0074 offset = <0x0>;
0075 mask = <0x1>;
0076 };
0077 };
0078
0079 periph_intc: interrupt-controller@fffe000c {
0080 compatible = "brcm,bcm6345-l1-intc";
0081 reg = <0xfffe000c 0x8>,
0082 <0xfffe0038 0x8>;
0083
0084 interrupt-controller;
0085 #interrupt-cells = <1>;
0086
0087 interrupt-parent = <&cpu_intc>;
0088 interrupts = <2>, <3>;
0089 };
0090
0091 periph_rst: reset-controller@fffe0034 {
0092 compatible = "brcm,bcm6345-reset";
0093 reg = <0xfffe0034 0x4>;
0094 #reset-cells = <1>;
0095 };
0096
0097 wdt: watchdog@fffe005c {
0098 compatible = "brcm,bcm7038-wdt";
0099 reg = <0xfffe005c 0xc>;
0100
0101 clocks = <&periph_osc>;
0102 clock-names = "refclk";
0103
0104 timeout-sec = <30>;
0105 };
0106
0107 leds0: led-controller@fffe00d0 {
0108 #address-cells = <1>;
0109 #size-cells = <0>;
0110 compatible = "brcm,bcm6358-leds";
0111 reg = <0xfffe00d0 0x8>;
0112
0113 status = "disabled";
0114 };
0115
0116 uart0: serial@fffe0100 {
0117 compatible = "brcm,bcm6345-uart";
0118 reg = <0xfffe0100 0x18>;
0119
0120 interrupt-parent = <&periph_intc>;
0121 interrupts = <2>;
0122
0123 clocks = <&periph_osc>;
0124 clock-names = "refclk";
0125
0126 status = "disabled";
0127 };
0128
0129 uart1: serial@fffe0120 {
0130 compatible = "brcm,bcm6345-uart";
0131 reg = <0xfffe0120 0x18>;
0132
0133 interrupt-parent = <&periph_intc>;
0134 interrupts = <3>;
0135
0136 clocks = <&periph_osc>;
0137 clock-names = "refclk";
0138
0139 status = "disabled";
0140 };
0141
0142 lsspi: spi@fffe0800 {
0143 #address-cells = <1>;
0144 #size-cells = <0>;
0145 compatible = "brcm,bcm6358-spi";
0146 reg = <0xfffe0800 0x70c>;
0147
0148 interrupt-parent = <&periph_intc>;
0149 interrupts = <1>;
0150
0151 clocks = <&periph_clk BCM6358_CLK_SPI>;
0152 clock-names = "spi";
0153
0154 resets = <&periph_rst BCM6358_RST_SPI>;
0155 reset-names = "spi";
0156
0157 status = "disabled";
0158 };
0159
0160 ehci: usb@fffe1300 {
0161 compatible = "brcm,bcm6358-ehci", "generic-ehci";
0162 reg = <0xfffe1300 0x100>;
0163 big-endian;
0164
0165 interrupt-parent = <&periph_intc>;
0166 interrupts = <10>;
0167
0168 phys = <&usbh 0>;
0169 phy-names = "usb";
0170
0171 status = "disabled";
0172 };
0173
0174 ohci: usb@fffe1400 {
0175 compatible = "brcm,bcm6358-ohci", "generic-ohci";
0176 reg = <0xfffe1400 0x100>;
0177 big-endian;
0178 no-big-frame-no;
0179
0180 interrupt-parent = <&periph_intc>;
0181 interrupts = <5>;
0182
0183 phys = <&usbh 0>;
0184 phy-names = "usb";
0185
0186 status = "disabled";
0187 };
0188
0189 usbh: usb-phy@fffe1500 {
0190 compatible = "brcm,bcm6358-usbh-phy";
0191 reg = <0xfffe1500 0x38>;
0192 #phy-cells = <1>;
0193
0194 resets = <&periph_rst BCM6358_RST_USBH>;
0195 reset-names = "usbh";
0196
0197 status = "disabled";
0198 };
0199 };
0200
0201 pflash: nor@1e000000 {
0202 #address-cells = <1>;
0203 #size-cells = <1>;
0204 compatible = "cfi-flash";
0205 reg = <0x1e000000 0x2000000>;
0206 bank-width = <2>;
0207
0208 status = "disabled";
0209 };
0210 };
