0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 #include "dt-bindings/clock/bcm3368-clock.h"
0004
0005 / {
0006 #address-cells = <1>;
0007 #size-cells = <1>;
0008 compatible = "brcm,bcm3368";
0009
0010 cpus {
0011 #address-cells = <1>;
0012 #size-cells = <0>;
0013
0014 mips-hpt-frequency = <150000000>;
0015
0016 cpu@0 {
0017 compatible = "brcm,bmips4350";
0018 device_type = "cpu";
0019 reg = <0>;
0020 };
0021
0022 cpu@1 {
0023 compatible = "brcm,bmips4350";
0024 device_type = "cpu";
0025 reg = <1>;
0026 };
0027 };
0028
0029 clocks {
0030 periph_clk: periph-clk {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <50000000>;
0034 };
0035 };
0036
0037 aliases {
0038 serial0 = &uart0;
0039 serial1 = &uart1;
0040 };
0041
0042 cpu_intc: interrupt-controller {
0043 #address-cells = <0>;
0044 compatible = "mti,cpu-interrupt-controller";
0045
0046 interrupt-controller;
0047 #interrupt-cells = <1>;
0048 };
0049
0050 ubus {
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053
0054 compatible = "simple-bus";
0055 ranges;
0056
0057 clkctl: clock-controller@fff8c004 {
0058 compatible = "brcm,bcm3368-clocks";
0059 reg = <0xfff8c004 0x4>;
0060 #clock-cells = <1>;
0061 };
0062
0063 periph_cntl: syscon@fff8c008 {
0064 compatible = "syscon";
0065 reg = <0xfff8c008 0x4>;
0066 native-endian;
0067 };
0068
0069 reboot: syscon-reboot@fff8c008 {
0070 compatible = "syscon-reboot";
0071 regmap = <&periph_cntl>;
0072 offset = <0x0>;
0073 mask = <0x1>;
0074 };
0075
0076 periph_intc: interrupt-controller@fff8c00c {
0077 compatible = "brcm,bcm6345-l1-intc";
0078 reg = <0xfff8c00c 0x8>;
0079
0080 interrupt-controller;
0081 #interrupt-cells = <1>;
0082
0083 interrupt-parent = <&cpu_intc>;
0084 interrupts = <2>;
0085 };
0086
0087 uart0: serial@fff8c100 {
0088 compatible = "brcm,bcm6345-uart";
0089 reg = <0xfff8c100 0x18>;
0090
0091 interrupt-parent = <&periph_intc>;
0092 interrupts = <2>;
0093
0094 clocks = <&periph_clk>;
0095 clock-names = "refclk";
0096
0097 status = "disabled";
0098 };
0099
0100 uart1: serial@fff8c120 {
0101 compatible = "brcm,bcm6345-uart";
0102 reg = <0xfff8c120 0x18>;
0103
0104 interrupt-parent = <&periph_intc>;
0105 interrupts = <3>;
0106
0107 clocks = <&periph_clk>;
0108 clock-names = "refclk";
0109
0110 status = "disabled";
0111 };
0112 };
0113 };
