mips/bcm63xx/cpu.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
0007  * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/export.h>
0012 #include <linux/cpu.h>
0013 #include <asm/cpu.h>
0014 #include <asm/cpu-info.h>
0015 #include <asm/mipsregs.h>
0016 #include <bcm63xx_cpu.h>
0017 #include <bcm63xx_regs.h>
0018 #include <bcm63xx_io.h>
0019 #include <bcm63xx_irq.h>
0020
0021 const unsigned long *bcm63xx_regs_base;
0022 EXPORT_SYMBOL(bcm63xx_regs_base);
0023
0024 const int *bcm63xx_irqs;
0025 EXPORT_SYMBOL(bcm63xx_irqs);
0026
0027 u16 bcm63xx_cpu_id __read_mostly;
0028 EXPORT_SYMBOL(bcm63xx_cpu_id);
0029
0030 static u8 bcm63xx_cpu_rev;
0031 static unsigned int bcm63xx_cpu_freq;
0032 static unsigned int bcm63xx_memory_size;
0033
0034 static const unsigned long bcm3368_regs_base[] = {
0035     __GEN_CPU_REGS_TABLE(3368)
0036 };
0037
0038 static const int bcm3368_irqs[] = {
0039     __GEN_CPU_IRQ_TABLE(3368)
0040 };
0041
0042 static const unsigned long bcm6328_regs_base[] = {
0043     __GEN_CPU_REGS_TABLE(6328)
0044 };
0045
0046 static const int bcm6328_irqs[] = {
0047     __GEN_CPU_IRQ_TABLE(6328)
0048 };
0049
0050 static const unsigned long bcm6338_regs_base[] = {
0051     __GEN_CPU_REGS_TABLE(6338)
0052 };
0053
0054 static const int bcm6338_irqs[] = {
0055     __GEN_CPU_IRQ_TABLE(6338)
0056 };
0057
0058 static const unsigned long bcm6345_regs_base[] = {
0059     __GEN_CPU_REGS_TABLE(6345)
0060 };
0061
0062 static const int bcm6345_irqs[] = {
0063     __GEN_CPU_IRQ_TABLE(6345)
0064 };
0065
0066 static const unsigned long bcm6348_regs_base[] = {
0067     __GEN_CPU_REGS_TABLE(6348)
0068 };
0069
0070 static const int bcm6348_irqs[] = {
0071     __GEN_CPU_IRQ_TABLE(6348)
0072
0073 };
0074
0075 static const unsigned long bcm6358_regs_base[] = {
0076     __GEN_CPU_REGS_TABLE(6358)
0077 };
0078
0079 static const int bcm6358_irqs[] = {
0080     __GEN_CPU_IRQ_TABLE(6358)
0081
0082 };
0083
0084 static const unsigned long bcm6362_regs_base[] = {
0085     __GEN_CPU_REGS_TABLE(6362)
0086 };
0087
0088 static const int bcm6362_irqs[] = {
0089     __GEN_CPU_IRQ_TABLE(6362)
0090
0091 };
0092
0093 static const unsigned long bcm6368_regs_base[] = {
0094     __GEN_CPU_REGS_TABLE(6368)
0095 };
0096
0097 static const int bcm6368_irqs[] = {
0098     __GEN_CPU_IRQ_TABLE(6368)
0099
0100 };
0101
0102 u8 bcm63xx_get_cpu_rev(void)
0103 {
0104     return bcm63xx_cpu_rev;
0105 }
0106
0107 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
0108
0109 unsigned int bcm63xx_get_cpu_freq(void)
0110 {
0111     return bcm63xx_cpu_freq;
0112 }
0113
0114 unsigned int bcm63xx_get_memory_size(void)
0115 {
0116     return bcm63xx_memory_size;
0117 }
0118
0119 static unsigned int detect_cpu_clock(void)
0120 {
0121     u16 cpu_id = bcm63xx_get_cpu_id();
0122
0123     switch (cpu_id) {
0124     case BCM3368_CPU_ID:
0125         return 300000000;
0126
0127     case BCM6328_CPU_ID:
0128     {
0129         unsigned int tmp, mips_pll_fcvo;
0130
0131         tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
0132         mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
0133                 >> STRAPBUS_6328_FCVO_SHIFT;
0134
0135         switch (mips_pll_fcvo) {
0136         case 0x12:
0137         case 0x14:
0138         case 0x19:
0139             return 160000000;
0140         case 0x1c:
0141             return 192000000;
0142         case 0x13:
0143         case 0x15:
0144             return 200000000;
0145         case 0x1a:
0146             return 384000000;
0147         case 0x16:
0148             return 400000000;
0149         default:
0150             return 320000000;
0151         }
0152
0153     }
0154     case BCM6338_CPU_ID:
0155         /* BCM6338 has a fixed 240 Mhz frequency */
0156         return 240000000;
0157
0158     case BCM6345_CPU_ID:
0159         /* BCM6345 has a fixed 140Mhz frequency */
0160         return 140000000;
0161
0162     case BCM6348_CPU_ID:
0163     {
0164         unsigned int tmp, n1, n2, m1;
0165
0166         /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
0167         tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
0168         n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
0169         n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
0170         m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
0171         n1 += 1;
0172         n2 += 2;
0173         m1 += 1;
0174         return (16 * 1000000 * n1 * n2) / m1;
0175     }
0176
0177     case BCM6358_CPU_ID:
0178     {
0179         unsigned int tmp, n1, n2, m1;
0180
0181         /* 16MHz * N1 * N2 / M1_CPU */
0182         tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
0183         n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
0184         n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
0185         m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
0186         return (16 * 1000000 * n1 * n2) / m1;
0187     }
0188
0189     case BCM6362_CPU_ID:
0190     {
0191         unsigned int tmp, mips_pll_fcvo;
0192
0193         tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
0194         mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
0195                 >> STRAPBUS_6362_FCVO_SHIFT;
0196         switch (mips_pll_fcvo) {
0197         case 0x03:
0198         case 0x0b:
0199         case 0x13:
0200         case 0x1b:
0201             return 240000000;
0202         case 0x04:
0203         case 0x0c:
0204         case 0x14:
0205         case 0x1c:
0206             return 160000000;
0207         case 0x05:
0208         case 0x0e:
0209         case 0x16:
0210         case 0x1e:
0211         case 0x1f:
0212             return 400000000;
0213         case 0x06:
0214             return 440000000;
0215         case 0x07:
0216         case 0x17:
0217             return 384000000;
0218         case 0x15:
0219         case 0x1d:
0220             return 200000000;
0221         default:
0222             return 320000000;
0223         }
0224     }
0225     case BCM6368_CPU_ID:
0226     {
0227         unsigned int tmp, p1, p2, ndiv, m1;
0228
0229         /* (64MHz / P1) * P2 * NDIV / M1_CPU */
0230         tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
0231
0232         p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
0233             DMIPSPLLCFG_6368_P1_SHIFT;
0234
0235         p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
0236             DMIPSPLLCFG_6368_P2_SHIFT;
0237
0238         ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
0239             DMIPSPLLCFG_6368_NDIV_SHIFT;
0240
0241         tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
0242         m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
0243             DMIPSPLLDIV_6368_MDIV_SHIFT;
0244
0245         return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
0246     }
0247
0248     default:
0249         panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
0250     }
0251 }
0252
0253 /*
0254  * attempt to detect the amount of memory installed
0255  */
0256 static unsigned int detect_memory_size(void)
0257 {
0258     unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
0259     u32 val;
0260
0261     if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
0262         return bcm_ddr_readl(DDR_CSEND_REG) << 24;
0263
0264     if (BCMCPU_IS_6345()) {
0265         val = bcm_sdram_readl(SDRAM_MBASE_REG);
0266         return val * 8 * 1024 * 1024;
0267     }
0268
0269     if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
0270         val = bcm_sdram_readl(SDRAM_CFG_REG);
0271         rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
0272         cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
0273         is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
0274         banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
0275     }
0276
0277     if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
0278         val = bcm_memc_readl(MEMC_CFG_REG);
0279         rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
0280         cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
0281         is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
0282         banks = 2;
0283     }
0284
0285     /* 0 => 11 address bits ... 2 => 13 address bits */
0286     rows += 11;
0287
0288     /* 0 => 8 address bits ... 2 => 10 address bits */
0289     cols += 8;
0290
0291     return 1 << (cols + rows + (is_32bits + 1) + banks);
0292 }
0293
0294 void __init bcm63xx_cpu_init(void)
0295 {
0296     unsigned int tmp;
0297     unsigned int cpu = smp_processor_id();
0298     u32 chipid_reg;
0299
0300     /* soc registers location depends on cpu type */
0301     chipid_reg = 0;
0302
0303     switch (current_cpu_type()) {
0304     case CPU_BMIPS3300:
0305         if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
0306             __cpu_name[cpu] = "Broadcom BCM6338";
0307         fallthrough;
0308     case CPU_BMIPS32:
0309         chipid_reg = BCM_6345_PERF_BASE;
0310         break;
0311     case CPU_BMIPS4350:
0312         switch ((read_c0_prid() & PRID_REV_MASK)) {
0313         case 0x04:
0314             chipid_reg = BCM_3368_PERF_BASE;
0315             break;
0316         case 0x10:
0317             chipid_reg = BCM_6345_PERF_BASE;
0318             break;
0319         default:
0320             chipid_reg = BCM_6368_PERF_BASE;
0321             break;
0322         }
0323         break;
0324     }
0325
0326     /*
0327      * really early to panic, but delaying panic would not help since we
0328      * will never get any working console
0329      */
0330     if (!chipid_reg)
0331         panic("unsupported Broadcom CPU");
0332
0333     /* read out CPU type */
0334     tmp = bcm_readl(chipid_reg);
0335     bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
0336     bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
0337
0338     switch (bcm63xx_cpu_id) {
0339     case BCM3368_CPU_ID:
0340         bcm63xx_regs_base = bcm3368_regs_base;
0341         bcm63xx_irqs = bcm3368_irqs;
0342         break;
0343     case BCM6328_CPU_ID:
0344         bcm63xx_regs_base = bcm6328_regs_base;
0345         bcm63xx_irqs = bcm6328_irqs;
0346         break;
0347     case BCM6338_CPU_ID:
0348         bcm63xx_regs_base = bcm6338_regs_base;
0349         bcm63xx_irqs = bcm6338_irqs;
0350         break;
0351     case BCM6345_CPU_ID:
0352         bcm63xx_regs_base = bcm6345_regs_base;
0353         bcm63xx_irqs = bcm6345_irqs;
0354         break;
0355     case BCM6348_CPU_ID:
0356         bcm63xx_regs_base = bcm6348_regs_base;
0357         bcm63xx_irqs = bcm6348_irqs;
0358         break;
0359     case BCM6358_CPU_ID:
0360         bcm63xx_regs_base = bcm6358_regs_base;
0361         bcm63xx_irqs = bcm6358_irqs;
0362         break;
0363     case BCM6362_CPU_ID:
0364         bcm63xx_regs_base = bcm6362_regs_base;
0365         bcm63xx_irqs = bcm6362_irqs;
0366         break;
0367     case BCM6368_CPU_ID:
0368         bcm63xx_regs_base = bcm6368_regs_base;
0369         bcm63xx_irqs = bcm6368_irqs;
0370         break;
0371     default:
0372         panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
0373         break;
0374     }
0375
0376     bcm63xx_cpu_freq = detect_cpu_clock();
0377     bcm63xx_memory_size = detect_memory_size();
0378
0379     pr_info("Detected Broadcom 0x%04x CPU revision %02x\n",
0380         bcm63xx_cpu_id, bcm63xx_cpu_rev);
0381     pr_info("CPU frequency is %u MHz\n",
0382         bcm63xx_cpu_freq / 1000000);
0383     pr_info("%uMB of RAM installed\n",
0384         bcm63xx_memory_size >> 20);
0385 }