mips/ath79/setup.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71XX/AR724X/AR913X specific setup
0004  *
0005  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
0006  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0007  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  *
0009  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/memblock.h>
0016 #include <linux/err.h>
0017 #include <linux/clk.h>
0018 #include <linux/of_clk.h>
0019 #include <linux/of_fdt.h>
0020 #include <linux/irqchip.h>
0021
0022 #include <asm/bootinfo.h>
0023 #include <asm/idle.h>
0024 #include <asm/time.h>       /* for mips_hpt_frequency */
0025 #include <asm/reboot.h>     /* for _machine_{restart,halt} */
0026 #include <asm/prom.h>
0027 #include <asm/fw/fw.h>
0028
0029 #include <asm/mach-ath79/ath79.h>
0030 #include <asm/mach-ath79/ar71xx_regs.h>
0031 #include "common.h"
0032
0033 #define ATH79_SYS_TYPE_LEN  64
0034
0035 static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
0036
0037 static void ath79_halt(void)
0038 {
0039     while (1)
0040         cpu_wait();
0041 }
0042
0043 static void __init ath79_detect_sys_type(void)
0044 {
0045     char *chip = "????";
0046     u32 id;
0047     u32 major;
0048     u32 minor;
0049     u32 rev = 0;
0050     u32 ver = 1;
0051
0052     id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
0053     major = id & REV_ID_MAJOR_MASK;
0054
0055     switch (major) {
0056     case REV_ID_MAJOR_AR71XX:
0057         minor = id & AR71XX_REV_ID_MINOR_MASK;
0058         rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
0059         rev &= AR71XX_REV_ID_REVISION_MASK;
0060         switch (minor) {
0061         case AR71XX_REV_ID_MINOR_AR7130:
0062             ath79_soc = ATH79_SOC_AR7130;
0063             chip = "7130";
0064             break;
0065
0066         case AR71XX_REV_ID_MINOR_AR7141:
0067             ath79_soc = ATH79_SOC_AR7141;
0068             chip = "7141";
0069             break;
0070
0071         case AR71XX_REV_ID_MINOR_AR7161:
0072             ath79_soc = ATH79_SOC_AR7161;
0073             chip = "7161";
0074             break;
0075         }
0076         break;
0077
0078     case REV_ID_MAJOR_AR7240:
0079         ath79_soc = ATH79_SOC_AR7240;
0080         chip = "7240";
0081         rev = id & AR724X_REV_ID_REVISION_MASK;
0082         break;
0083
0084     case REV_ID_MAJOR_AR7241:
0085         ath79_soc = ATH79_SOC_AR7241;
0086         chip = "7241";
0087         rev = id & AR724X_REV_ID_REVISION_MASK;
0088         break;
0089
0090     case REV_ID_MAJOR_AR7242:
0091         ath79_soc = ATH79_SOC_AR7242;
0092         chip = "7242";
0093         rev = id & AR724X_REV_ID_REVISION_MASK;
0094         break;
0095
0096     case REV_ID_MAJOR_AR913X:
0097         minor = id & AR913X_REV_ID_MINOR_MASK;
0098         rev = id >> AR913X_REV_ID_REVISION_SHIFT;
0099         rev &= AR913X_REV_ID_REVISION_MASK;
0100         switch (minor) {
0101         case AR913X_REV_ID_MINOR_AR9130:
0102             ath79_soc = ATH79_SOC_AR9130;
0103             chip = "9130";
0104             break;
0105
0106         case AR913X_REV_ID_MINOR_AR9132:
0107             ath79_soc = ATH79_SOC_AR9132;
0108             chip = "9132";
0109             break;
0110         }
0111         break;
0112
0113     case REV_ID_MAJOR_AR9330:
0114         ath79_soc = ATH79_SOC_AR9330;
0115         chip = "9330";
0116         rev = id & AR933X_REV_ID_REVISION_MASK;
0117         break;
0118
0119     case REV_ID_MAJOR_AR9331:
0120         ath79_soc = ATH79_SOC_AR9331;
0121         chip = "9331";
0122         rev = id & AR933X_REV_ID_REVISION_MASK;
0123         break;
0124
0125     case REV_ID_MAJOR_AR9341:
0126         ath79_soc = ATH79_SOC_AR9341;
0127         chip = "9341";
0128         rev = id & AR934X_REV_ID_REVISION_MASK;
0129         break;
0130
0131     case REV_ID_MAJOR_AR9342:
0132         ath79_soc = ATH79_SOC_AR9342;
0133         chip = "9342";
0134         rev = id & AR934X_REV_ID_REVISION_MASK;
0135         break;
0136
0137     case REV_ID_MAJOR_AR9344:
0138         ath79_soc = ATH79_SOC_AR9344;
0139         chip = "9344";
0140         rev = id & AR934X_REV_ID_REVISION_MASK;
0141         break;
0142
0143     case REV_ID_MAJOR_QCA9533_V2:
0144         ver = 2;
0145         ath79_soc_rev = 2;
0146         fallthrough;
0147     case REV_ID_MAJOR_QCA9533:
0148         ath79_soc = ATH79_SOC_QCA9533;
0149         chip = "9533";
0150         rev = id & QCA953X_REV_ID_REVISION_MASK;
0151         break;
0152
0153     case REV_ID_MAJOR_QCA9556:
0154         ath79_soc = ATH79_SOC_QCA9556;
0155         chip = "9556";
0156         rev = id & QCA955X_REV_ID_REVISION_MASK;
0157         break;
0158
0159     case REV_ID_MAJOR_QCA9558:
0160         ath79_soc = ATH79_SOC_QCA9558;
0161         chip = "9558";
0162         rev = id & QCA955X_REV_ID_REVISION_MASK;
0163         break;
0164
0165     case REV_ID_MAJOR_QCA956X:
0166         ath79_soc = ATH79_SOC_QCA956X;
0167         chip = "956X";
0168         rev = id & QCA956X_REV_ID_REVISION_MASK;
0169         break;
0170
0171     case REV_ID_MAJOR_QCN550X:
0172         ath79_soc = ATH79_SOC_QCA956X;
0173         chip = "550X";
0174         rev = id & QCA956X_REV_ID_REVISION_MASK;
0175         break;
0176
0177     case REV_ID_MAJOR_TP9343:
0178         ath79_soc = ATH79_SOC_TP9343;
0179         chip = "9343";
0180         rev = id & QCA956X_REV_ID_REVISION_MASK;
0181         break;
0182
0183     default:
0184         panic("ath79: unknown SoC, id:0x%08x", id);
0185     }
0186
0187     if (ver == 1)
0188         ath79_soc_rev = rev;
0189
0190     if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
0191         sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
0192             chip, ver, rev);
0193     else if (soc_is_tp9343())
0194         sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
0195             chip, rev);
0196     else
0197         sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
0198     pr_info("SoC: %s\n", ath79_sys_type);
0199 }
0200
0201 const char *get_system_type(void)
0202 {
0203     return ath79_sys_type;
0204 }
0205
0206 unsigned int get_c0_compare_int(void)
0207 {
0208     return CP0_LEGACY_COMPARE_IRQ;
0209 }
0210
0211 void __init plat_mem_setup(void)
0212 {
0213     void *dtb;
0214
0215     set_io_port_base(KSEG1);
0216
0217     /* Get the position of the FDT passed by the bootloader */
0218     dtb = (void *)fw_getenvl("fdt_start");
0219     if (dtb == NULL)
0220         dtb = get_fdt();
0221
0222     if (dtb)
0223         __dt_setup_arch((void *)KSEG0ADDR(dtb));
0224
0225     ath79_reset_base = ioremap(AR71XX_RESET_BASE,
0226                        AR71XX_RESET_SIZE);
0227     ath79_pll_base = ioremap(AR71XX_PLL_BASE,
0228                      AR71XX_PLL_SIZE);
0229     ath79_detect_sys_type();
0230     ath79_ddr_ctrl_init();
0231
0232     detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
0233
0234     _machine_halt = ath79_halt;
0235     pm_power_off = ath79_halt;
0236 }
0237
0238 void __init plat_time_init(void)
0239 {
0240     struct device_node *np;
0241     struct clk *clk;
0242     unsigned long cpu_clk_rate;
0243
0244     of_clk_init(NULL);
0245
0246     np = of_get_cpu_node(0, NULL);
0247     if (!np) {
0248         pr_err("Failed to get CPU node\n");
0249         return;
0250     }
0251
0252     clk = of_clk_get(np, 0);
0253     if (IS_ERR(clk)) {
0254         pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
0255         return;
0256     }
0257
0258     cpu_clk_rate = clk_get_rate(clk);
0259
0260     pr_info("CPU clock: %lu.%03lu MHz\n",
0261         cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
0262
0263     mips_hpt_frequency = cpu_clk_rate / 2;
0264
0265     clk_put(clk);
0266 }
0267
0268 void __init arch_init_irq(void)
0269 {
0270     irqchip_init();
0271 }