mips/ath79/common.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71XX/AR724X/AR913X common routines
0004  *
0005  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
0006  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0007  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  *
0009  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/export.h>
0014 #include <linux/types.h>
0015 #include <linux/spinlock.h>
0016
0017 #include <asm/mach-ath79/ath79.h>
0018 #include <asm/mach-ath79/ar71xx_regs.h>
0019 #include "common.h"
0020
0021 static DEFINE_SPINLOCK(ath79_device_reset_lock);
0022
0023 u32 ath79_cpu_freq;
0024 EXPORT_SYMBOL_GPL(ath79_cpu_freq);
0025
0026 u32 ath79_ahb_freq;
0027 EXPORT_SYMBOL_GPL(ath79_ahb_freq);
0028
0029 u32 ath79_ddr_freq;
0030 EXPORT_SYMBOL_GPL(ath79_ddr_freq);
0031
0032 enum ath79_soc_type ath79_soc;
0033 unsigned int ath79_soc_rev;
0034
0035 void __iomem *ath79_pll_base;
0036 void __iomem *ath79_reset_base;
0037 EXPORT_SYMBOL_GPL(ath79_reset_base);
0038 static void __iomem *ath79_ddr_base;
0039 static void __iomem *ath79_ddr_wb_flush_base;
0040 static void __iomem *ath79_ddr_pci_win_base;
0041
0042 void ath79_ddr_ctrl_init(void)
0043 {
0044     ath79_ddr_base = ioremap(AR71XX_DDR_CTRL_BASE,
0045                      AR71XX_DDR_CTRL_SIZE);
0046     if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
0047         ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
0048         ath79_ddr_pci_win_base = 0;
0049     } else {
0050         ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
0051         ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
0052     }
0053 }
0054 EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
0055
0056 void ath79_ddr_wb_flush(u32 reg)
0057 {
0058     void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
0059
0060     /* Flush the DDR write buffer. */
0061     __raw_writel(0x1, flush_reg);
0062     while (__raw_readl(flush_reg) & 0x1)
0063         ;
0064
0065     /* It must be run twice. */
0066     __raw_writel(0x1, flush_reg);
0067     while (__raw_readl(flush_reg) & 0x1)
0068         ;
0069 }
0070 EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
0071
0072 void ath79_ddr_set_pci_windows(void)
0073 {
0074     BUG_ON(!ath79_ddr_pci_win_base);
0075
0076     __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
0077     __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
0078     __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
0079     __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
0080     __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
0081     __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
0082     __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
0083     __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
0084 }
0085 EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
0086
0087 void ath79_device_reset_set(u32 mask)
0088 {
0089     unsigned long flags;
0090     u32 reg;
0091     u32 t;
0092
0093     if (soc_is_ar71xx())
0094         reg = AR71XX_RESET_REG_RESET_MODULE;
0095     else if (soc_is_ar724x())
0096         reg = AR724X_RESET_REG_RESET_MODULE;
0097     else if (soc_is_ar913x())
0098         reg = AR913X_RESET_REG_RESET_MODULE;
0099     else if (soc_is_ar933x())
0100         reg = AR933X_RESET_REG_RESET_MODULE;
0101     else if (soc_is_ar934x())
0102         reg = AR934X_RESET_REG_RESET_MODULE;
0103     else if (soc_is_qca953x())
0104         reg = QCA953X_RESET_REG_RESET_MODULE;
0105     else if (soc_is_qca955x())
0106         reg = QCA955X_RESET_REG_RESET_MODULE;
0107     else if (soc_is_qca956x() || soc_is_tp9343())
0108         reg = QCA956X_RESET_REG_RESET_MODULE;
0109     else
0110         BUG();
0111
0112     spin_lock_irqsave(&ath79_device_reset_lock, flags);
0113     t = ath79_reset_rr(reg);
0114     ath79_reset_wr(reg, t | mask);
0115     spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
0116 }
0117 EXPORT_SYMBOL_GPL(ath79_device_reset_set);
0118
0119 void ath79_device_reset_clear(u32 mask)
0120 {
0121     unsigned long flags;
0122     u32 reg;
0123     u32 t;
0124
0125     if (soc_is_ar71xx())
0126         reg = AR71XX_RESET_REG_RESET_MODULE;
0127     else if (soc_is_ar724x())
0128         reg = AR724X_RESET_REG_RESET_MODULE;
0129     else if (soc_is_ar913x())
0130         reg = AR913X_RESET_REG_RESET_MODULE;
0131     else if (soc_is_ar933x())
0132         reg = AR933X_RESET_REG_RESET_MODULE;
0133     else if (soc_is_ar934x())
0134         reg = AR934X_RESET_REG_RESET_MODULE;
0135     else if (soc_is_qca953x())
0136         reg = QCA953X_RESET_REG_RESET_MODULE;
0137     else if (soc_is_qca955x())
0138         reg = QCA955X_RESET_REG_RESET_MODULE;
0139     else if (soc_is_qca956x() || soc_is_tp9343())
0140         reg = QCA956X_RESET_REG_RESET_MODULE;
0141     else
0142         BUG();
0143
0144     spin_lock_irqsave(&ath79_device_reset_lock, flags);
0145     t = ath79_reset_rr(reg);
0146     ath79_reset_wr(reg, t & ~mask);
0147     spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
0148 }
0149 EXPORT_SYMBOL_GPL(ath79_device_reset_clear);