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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71XX/AR724X/AR913X common routines
0004  *
0005  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
0006  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
0007  *
0008  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/io.h>
0014 #include <linux/err.h>
0015 #include <linux/clk.h>
0016 #include <linux/clkdev.h>
0017 #include <linux/clk-provider.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <dt-bindings/clock/ath79-clk.h>
0021 
0022 #include <asm/div64.h>
0023 
0024 #include <asm/mach-ath79/ath79.h>
0025 #include <asm/mach-ath79/ar71xx_regs.h>
0026 #include "common.h"
0027 
0028 #define AR71XX_BASE_FREQ    40000000
0029 #define AR724X_BASE_FREQ    40000000
0030 
0031 static struct clk *clks[ATH79_CLK_END];
0032 static struct clk_onecell_data clk_data = {
0033     .clks = clks,
0034     .clk_num = ARRAY_SIZE(clks),
0035 };
0036 
0037 static const char * const clk_names[ATH79_CLK_END] = {
0038     [ATH79_CLK_CPU] = "cpu",
0039     [ATH79_CLK_DDR] = "ddr",
0040     [ATH79_CLK_AHB] = "ahb",
0041     [ATH79_CLK_REF] = "ref",
0042     [ATH79_CLK_MDIO] = "mdio",
0043 };
0044 
0045 static const char * __init ath79_clk_name(int type)
0046 {
0047     BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
0048     return clk_names[type];
0049 }
0050 
0051 static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
0052 {
0053     if (IS_ERR(clk))
0054         panic("failed to allocate %s clock structure", clk_names[type]);
0055 
0056     clks[type] = clk;
0057     clk_register_clkdev(clk, name, NULL);
0058 }
0059 
0060 static struct clk * __init ath79_set_clk(int type, unsigned long rate)
0061 {
0062     const char *name = ath79_clk_name(type);
0063     struct clk *clk;
0064 
0065     clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
0066     __ath79_set_clk(type, name, clk);
0067     return clk;
0068 }
0069 
0070 static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
0071                         unsigned int mult, unsigned int div)
0072 {
0073     const char *name = ath79_clk_name(type);
0074     struct clk *clk;
0075 
0076     clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
0077     __ath79_set_clk(type, name, clk);
0078     return clk;
0079 }
0080 
0081 static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
0082 {
0083     struct clk *clk = clks[ATH79_CLK_REF];
0084 
0085     if (clk)
0086         rate = clk_get_rate(clk);
0087     else
0088         clk = ath79_set_clk(ATH79_CLK_REF, rate);
0089 
0090     return rate;
0091 }
0092 
0093 static void __init ar71xx_clocks_init(void __iomem *pll_base)
0094 {
0095     unsigned long ref_rate;
0096     unsigned long cpu_rate;
0097     unsigned long ddr_rate;
0098     unsigned long ahb_rate;
0099     u32 pll;
0100     u32 freq;
0101     u32 div;
0102 
0103     ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
0104 
0105     pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
0106 
0107     div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
0108     freq = div * ref_rate;
0109 
0110     div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
0111     cpu_rate = freq / div;
0112 
0113     div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
0114     ddr_rate = freq / div;
0115 
0116     div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
0117     ahb_rate = cpu_rate / div;
0118 
0119     ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
0120     ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
0121     ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
0122 }
0123 
0124 static void __init ar724x_clocks_init(void __iomem *pll_base)
0125 {
0126     u32 mult, div, ddr_div, ahb_div;
0127     u32 pll;
0128 
0129     ath79_setup_ref_clk(AR71XX_BASE_FREQ);
0130 
0131     pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
0132 
0133     mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
0134     div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
0135 
0136     ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
0137     ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
0138 
0139     ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
0140     ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
0141     ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
0142 }
0143 
0144 static void __init ar933x_clocks_init(void __iomem *pll_base)
0145 {
0146     unsigned long ref_rate;
0147     u32 clock_ctrl;
0148     u32 ref_div;
0149     u32 ninit_mul;
0150     u32 out_div;
0151 
0152     u32 cpu_div;
0153     u32 ddr_div;
0154     u32 ahb_div;
0155     u32 t;
0156 
0157     t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
0158     if (t & AR933X_BOOTSTRAP_REF_CLK_40)
0159         ref_rate = (40 * 1000 * 1000);
0160     else
0161         ref_rate = (25 * 1000 * 1000);
0162 
0163     ath79_setup_ref_clk(ref_rate);
0164 
0165     clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
0166     if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
0167         ref_div = 1;
0168         ninit_mul = 1;
0169         out_div = 1;
0170 
0171         cpu_div = 1;
0172         ddr_div = 1;
0173         ahb_div = 1;
0174     } else {
0175         u32 cpu_config;
0176         u32 t;
0177 
0178         cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
0179 
0180         t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
0181             AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
0182         ref_div = t;
0183 
0184         ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
0185             AR933X_PLL_CPU_CONFIG_NINT_MASK;
0186 
0187         t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
0188             AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
0189         if (t == 0)
0190             t = 1;
0191 
0192         out_div = (1 << t);
0193 
0194         cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
0195              AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
0196 
0197         ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
0198               AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
0199 
0200         ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
0201              AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
0202     }
0203 
0204     ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
0205              ref_div * out_div * cpu_div);
0206     ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
0207              ref_div * out_div * ddr_div);
0208     ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
0209              ref_div * out_div * ahb_div);
0210 }
0211 
0212 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
0213                       u32 frac, u32 out_div)
0214 {
0215     u64 t;
0216     u32 ret;
0217 
0218     t = ref;
0219     t *= nint;
0220     do_div(t, ref_div);
0221     ret = t;
0222 
0223     t = ref;
0224     t *= nfrac;
0225     do_div(t, ref_div * frac);
0226     ret += t;
0227 
0228     ret /= (1 << out_div);
0229     return ret;
0230 }
0231 
0232 static void __init ar934x_clocks_init(void __iomem *pll_base)
0233 {
0234     unsigned long ref_rate;
0235     unsigned long cpu_rate;
0236     unsigned long ddr_rate;
0237     unsigned long ahb_rate;
0238     u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
0239     u32 cpu_pll, ddr_pll;
0240     u32 bootstrap;
0241     void __iomem *dpll_base;
0242 
0243     dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
0244 
0245     bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
0246     if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
0247         ref_rate = 40 * 1000 * 1000;
0248     else
0249         ref_rate = 25 * 1000 * 1000;
0250 
0251     ref_rate = ath79_setup_ref_clk(ref_rate);
0252 
0253     pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
0254     if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
0255         out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
0256               AR934X_SRIF_DPLL2_OUTDIV_MASK;
0257         pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
0258         nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
0259                AR934X_SRIF_DPLL1_NINT_MASK;
0260         nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
0261         ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
0262               AR934X_SRIF_DPLL1_REFDIV_MASK;
0263         frac = 1 << 18;
0264     } else {
0265         pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
0266         out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
0267             AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
0268         ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
0269               AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
0270         nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
0271                AR934X_PLL_CPU_CONFIG_NINT_MASK;
0272         nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
0273             AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
0274         frac = 1 << 6;
0275     }
0276 
0277     cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
0278                       nfrac, frac, out_div);
0279 
0280     pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
0281     if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
0282         out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
0283               AR934X_SRIF_DPLL2_OUTDIV_MASK;
0284         pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
0285         nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
0286                AR934X_SRIF_DPLL1_NINT_MASK;
0287         nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
0288         ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
0289               AR934X_SRIF_DPLL1_REFDIV_MASK;
0290         frac = 1 << 18;
0291     } else {
0292         pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
0293         out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
0294               AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
0295         ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
0296                AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
0297         nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
0298                AR934X_PLL_DDR_CONFIG_NINT_MASK;
0299         nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
0300             AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
0301         frac = 1 << 10;
0302     }
0303 
0304     ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
0305                       nfrac, frac, out_div);
0306 
0307     clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
0308 
0309     postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
0310           AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
0311 
0312     if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
0313         cpu_rate = ref_rate;
0314     else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
0315         cpu_rate = cpu_pll / (postdiv + 1);
0316     else
0317         cpu_rate = ddr_pll / (postdiv + 1);
0318 
0319     postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
0320           AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
0321 
0322     if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
0323         ddr_rate = ref_rate;
0324     else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
0325         ddr_rate = ddr_pll / (postdiv + 1);
0326     else
0327         ddr_rate = cpu_pll / (postdiv + 1);
0328 
0329     postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
0330           AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
0331 
0332     if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
0333         ahb_rate = ref_rate;
0334     else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
0335         ahb_rate = ddr_pll / (postdiv + 1);
0336     else
0337         ahb_rate = cpu_pll / (postdiv + 1);
0338 
0339     ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
0340     ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
0341     ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
0342 
0343     clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
0344     if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
0345         ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
0346 
0347     iounmap(dpll_base);
0348 }
0349 
0350 static void __init qca953x_clocks_init(void __iomem *pll_base)
0351 {
0352     unsigned long ref_rate;
0353     unsigned long cpu_rate;
0354     unsigned long ddr_rate;
0355     unsigned long ahb_rate;
0356     u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
0357     u32 cpu_pll, ddr_pll;
0358     u32 bootstrap;
0359 
0360     bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
0361     if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
0362         ref_rate = 40 * 1000 * 1000;
0363     else
0364         ref_rate = 25 * 1000 * 1000;
0365 
0366     ref_rate = ath79_setup_ref_clk(ref_rate);
0367 
0368     pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
0369     out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
0370           QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
0371     ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
0372           QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
0373     nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
0374            QCA953X_PLL_CPU_CONFIG_NINT_MASK;
0375     frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
0376            QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
0377 
0378     cpu_pll = nint * ref_rate / ref_div;
0379     cpu_pll += frac * (ref_rate >> 6) / ref_div;
0380     cpu_pll /= (1 << out_div);
0381 
0382     pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
0383     out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
0384           QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
0385     ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
0386           QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
0387     nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
0388            QCA953X_PLL_DDR_CONFIG_NINT_MASK;
0389     frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
0390            QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
0391 
0392     ddr_pll = nint * ref_rate / ref_div;
0393     ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
0394     ddr_pll /= (1 << out_div);
0395 
0396     clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
0397 
0398     postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
0399           QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
0400 
0401     if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
0402         cpu_rate = ref_rate;
0403     else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
0404         cpu_rate = cpu_pll / (postdiv + 1);
0405     else
0406         cpu_rate = ddr_pll / (postdiv + 1);
0407 
0408     postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
0409           QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
0410 
0411     if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
0412         ddr_rate = ref_rate;
0413     else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
0414         ddr_rate = ddr_pll / (postdiv + 1);
0415     else
0416         ddr_rate = cpu_pll / (postdiv + 1);
0417 
0418     postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
0419           QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
0420 
0421     if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
0422         ahb_rate = ref_rate;
0423     else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
0424         ahb_rate = ddr_pll / (postdiv + 1);
0425     else
0426         ahb_rate = cpu_pll / (postdiv + 1);
0427 
0428     ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
0429     ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
0430     ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
0431 }
0432 
0433 static void __init qca955x_clocks_init(void __iomem *pll_base)
0434 {
0435     unsigned long ref_rate;
0436     unsigned long cpu_rate;
0437     unsigned long ddr_rate;
0438     unsigned long ahb_rate;
0439     u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
0440     u32 cpu_pll, ddr_pll;
0441     u32 bootstrap;
0442 
0443     bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
0444     if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
0445         ref_rate = 40 * 1000 * 1000;
0446     else
0447         ref_rate = 25 * 1000 * 1000;
0448 
0449     ref_rate = ath79_setup_ref_clk(ref_rate);
0450 
0451     pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
0452     out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
0453           QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
0454     ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
0455           QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
0456     nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
0457            QCA955X_PLL_CPU_CONFIG_NINT_MASK;
0458     frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
0459            QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
0460 
0461     cpu_pll = nint * ref_rate / ref_div;
0462     cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
0463     cpu_pll /= (1 << out_div);
0464 
0465     pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
0466     out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
0467           QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
0468     ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
0469           QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
0470     nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
0471            QCA955X_PLL_DDR_CONFIG_NINT_MASK;
0472     frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
0473            QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
0474 
0475     ddr_pll = nint * ref_rate / ref_div;
0476     ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
0477     ddr_pll /= (1 << out_div);
0478 
0479     clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
0480 
0481     postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
0482           QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
0483 
0484     if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
0485         cpu_rate = ref_rate;
0486     else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
0487         cpu_rate = ddr_pll / (postdiv + 1);
0488     else
0489         cpu_rate = cpu_pll / (postdiv + 1);
0490 
0491     postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
0492           QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
0493 
0494     if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
0495         ddr_rate = ref_rate;
0496     else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
0497         ddr_rate = cpu_pll / (postdiv + 1);
0498     else
0499         ddr_rate = ddr_pll / (postdiv + 1);
0500 
0501     postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
0502           QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
0503 
0504     if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
0505         ahb_rate = ref_rate;
0506     else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
0507         ahb_rate = ddr_pll / (postdiv + 1);
0508     else
0509         ahb_rate = cpu_pll / (postdiv + 1);
0510 
0511     ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
0512     ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
0513     ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
0514 }
0515 
0516 static void __init qca956x_clocks_init(void __iomem *pll_base)
0517 {
0518     unsigned long ref_rate;
0519     unsigned long cpu_rate;
0520     unsigned long ddr_rate;
0521     unsigned long ahb_rate;
0522     u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
0523     u32 cpu_pll, ddr_pll;
0524     u32 bootstrap;
0525 
0526     /*
0527      * QCA956x timer init workaround has to be applied right before setting
0528      * up the clock. Else, there will be no jiffies
0529      */
0530     u32 misc;
0531 
0532     misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
0533     misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
0534     ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
0535 
0536     bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
0537     if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
0538         ref_rate = 40 * 1000 * 1000;
0539     else
0540         ref_rate = 25 * 1000 * 1000;
0541 
0542     ref_rate = ath79_setup_ref_clk(ref_rate);
0543 
0544     pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
0545     out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
0546           QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
0547     ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
0548           QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
0549 
0550     pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
0551     nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
0552            QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
0553     hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
0554            QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
0555     lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
0556            QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
0557 
0558     cpu_pll = nint * ref_rate / ref_div;
0559     cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
0560     cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
0561     cpu_pll /= (1 << out_div);
0562 
0563     pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
0564     out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
0565           QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
0566     ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
0567           QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
0568     pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
0569     nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
0570            QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
0571     hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
0572            QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
0573     lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
0574            QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
0575 
0576     ddr_pll = nint * ref_rate / ref_div;
0577     ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
0578     ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
0579     ddr_pll /= (1 << out_div);
0580 
0581     clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
0582 
0583     postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
0584           QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
0585 
0586     if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
0587         cpu_rate = ref_rate;
0588     else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
0589         cpu_rate = ddr_pll / (postdiv + 1);
0590     else
0591         cpu_rate = cpu_pll / (postdiv + 1);
0592 
0593     postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
0594           QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
0595 
0596     if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
0597         ddr_rate = ref_rate;
0598     else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
0599         ddr_rate = cpu_pll / (postdiv + 1);
0600     else
0601         ddr_rate = ddr_pll / (postdiv + 1);
0602 
0603     postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
0604           QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
0605 
0606     if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
0607         ahb_rate = ref_rate;
0608     else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
0609         ahb_rate = ddr_pll / (postdiv + 1);
0610     else
0611         ahb_rate = cpu_pll / (postdiv + 1);
0612 
0613     ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
0614     ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
0615     ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
0616 }
0617 
0618 static void __init ath79_clocks_init_dt(struct device_node *np)
0619 {
0620     struct clk *ref_clk;
0621     void __iomem *pll_base;
0622 
0623     ref_clk = of_clk_get(np, 0);
0624     if (!IS_ERR(ref_clk))
0625         clks[ATH79_CLK_REF] = ref_clk;
0626 
0627     pll_base = of_iomap(np, 0);
0628     if (!pll_base) {
0629         pr_err("%pOF: can't map pll registers\n", np);
0630         goto err_clk;
0631     }
0632 
0633     if (of_device_is_compatible(np, "qca,ar7100-pll"))
0634         ar71xx_clocks_init(pll_base);
0635     else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
0636          of_device_is_compatible(np, "qca,ar9130-pll"))
0637         ar724x_clocks_init(pll_base);
0638     else if (of_device_is_compatible(np, "qca,ar9330-pll"))
0639         ar933x_clocks_init(pll_base);
0640     else if (of_device_is_compatible(np, "qca,ar9340-pll"))
0641         ar934x_clocks_init(pll_base);
0642     else if (of_device_is_compatible(np, "qca,qca9530-pll"))
0643         qca953x_clocks_init(pll_base);
0644     else if (of_device_is_compatible(np, "qca,qca9550-pll"))
0645         qca955x_clocks_init(pll_base);
0646     else if (of_device_is_compatible(np, "qca,qca9560-pll"))
0647         qca956x_clocks_init(pll_base);
0648 
0649     if (!clks[ATH79_CLK_MDIO])
0650         clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
0651 
0652     if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
0653         pr_err("%pOF: could not register clk provider\n", np);
0654         goto err_iounmap;
0655     }
0656 
0657     return;
0658 
0659 err_iounmap:
0660     iounmap(pll_base);
0661 
0662 err_clk:
0663     clk_put(ref_clk);
0664 }
0665 
0666 CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
0667 CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
0668 CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
0669 CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
0670 CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
0671 CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
0672 CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
0673 CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
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