mips/ath25/ar5312_regs.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
0007  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
0008  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
0009  */
0010
0011 #ifndef __ASM_MACH_ATH25_AR5312_REGS_H
0012 #define __ASM_MACH_ATH25_AR5312_REGS_H
0013
0014 /*
0015  * IRQs
0016  */
0017 #define AR5312_IRQ_WLAN0    (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
0018 #define AR5312_IRQ_ENET0    (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
0019 #define AR5312_IRQ_ENET1    (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
0020 #define AR5312_IRQ_WLAN1    (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
0021 #define AR5312_IRQ_MISC     (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
0022
0023 /*
0024  * Miscellaneous interrupts, which share IP6.
0025  */
0026 #define AR5312_MISC_IRQ_TIMER       0
0027 #define AR5312_MISC_IRQ_AHB_PROC    1
0028 #define AR5312_MISC_IRQ_AHB_DMA     2
0029 #define AR5312_MISC_IRQ_GPIO        3
0030 #define AR5312_MISC_IRQ_UART0       4
0031 #define AR5312_MISC_IRQ_UART0_DMA   5
0032 #define AR5312_MISC_IRQ_WATCHDOG    6
0033 #define AR5312_MISC_IRQ_LOCAL       7
0034 #define AR5312_MISC_IRQ_SPI     8
0035 #define AR5312_MISC_IRQ_COUNT       9
0036
0037 /*
0038  * Address Map
0039  *
0040  * The AR5312 supports 2 enet MACS, even though many reference boards only
0041  * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
0042  * PHY or PHY switch. The AR2312 supports 1 enet MAC.
0043  */
0044 #define AR5312_WLAN0_BASE       0x18000000
0045 #define AR5312_ENET0_BASE       0x18100000
0046 #define AR5312_ENET1_BASE       0x18200000
0047 #define AR5312_SDRAMCTL_BASE        0x18300000
0048 #define AR5312_SDRAMCTL_SIZE        0x00000010
0049 #define AR5312_FLASHCTL_BASE        0x18400000
0050 #define AR5312_FLASHCTL_SIZE        0x00000010
0051 #define AR5312_WLAN1_BASE       0x18500000
0052 #define AR5312_UART0_BASE       0x1c000000  /* UART MMR */
0053 #define AR5312_GPIO_BASE        0x1c002000
0054 #define AR5312_GPIO_SIZE        0x00000010
0055 #define AR5312_RST_BASE         0x1c003000
0056 #define AR5312_RST_SIZE         0x00000100
0057 #define AR5312_FLASH_BASE       0x1e000000
0058 #define AR5312_FLASH_SIZE       0x00800000
0059
0060 /*
0061  * Need these defines to determine true number of ethernet MACs
0062  */
0063 #define AR5312_AR5312_REV2  0x0052      /* AR5312 WMAC (AP31) */
0064 #define AR5312_AR5312_REV7  0x0057      /* AR5312 WMAC (AP30-040) */
0065 #define AR5312_AR2313_REV8  0x0058      /* AR2313 WMAC (AP43-030) */
0066
0067 /* Reset/Timer Block Address Map */
0068 #define AR5312_TIMER        0x0000 /* countdown timer */
0069 #define AR5312_RELOAD       0x0004 /* timer reload value */
0070 #define AR5312_WDT_CTRL     0x0008 /* watchdog cntrl */
0071 #define AR5312_WDT_TIMER    0x000c /* watchdog timer */
0072 #define AR5312_ISR      0x0010 /* Intr Status Reg */
0073 #define AR5312_IMR      0x0014 /* Intr Mask Reg */
0074 #define AR5312_RESET        0x0020
0075 #define AR5312_CLOCKCTL1    0x0064
0076 #define AR5312_SCRATCH      0x006c
0077 #define AR5312_PROCADDR     0x0070
0078 #define AR5312_PROC1        0x0074
0079 #define AR5312_DMAADDR      0x0078
0080 #define AR5312_DMA1     0x007c
0081 #define AR5312_ENABLE       0x0080 /* interface enb */
0082 #define AR5312_REV      0x0090 /* revision */
0083
0084 /* AR5312_WDT_CTRL register bit field definitions */
0085 #define AR5312_WDT_CTRL_IGNORE  0x00000000  /* ignore expiration */
0086 #define AR5312_WDT_CTRL_NMI 0x00000001
0087 #define AR5312_WDT_CTRL_RESET   0x00000002
0088
0089 /* AR5312_ISR register bit field definitions */
0090 #define AR5312_ISR_TIMER    0x00000001
0091 #define AR5312_ISR_AHBPROC  0x00000002
0092 #define AR5312_ISR_AHBDMA   0x00000004
0093 #define AR5312_ISR_GPIO     0x00000008
0094 #define AR5312_ISR_UART0    0x00000010
0095 #define AR5312_ISR_UART0DMA 0x00000020
0096 #define AR5312_ISR_WD       0x00000040
0097 #define AR5312_ISR_LOCAL    0x00000080
0098
0099 /* AR5312_RESET register bit field definitions */
0100 #define AR5312_RESET_SYSTEM     0x00000001  /* cold reset full system */
0101 #define AR5312_RESET_PROC       0x00000002  /* cold reset MIPS core */
0102 #define AR5312_RESET_WLAN0      0x00000004  /* cold reset WLAN MAC/BB */
0103 #define AR5312_RESET_EPHY0      0x00000008  /* cold reset ENET0 phy */
0104 #define AR5312_RESET_EPHY1      0x00000010  /* cold reset ENET1 phy */
0105 #define AR5312_RESET_ENET0      0x00000020  /* cold reset ENET0 MAC */
0106 #define AR5312_RESET_ENET1      0x00000040  /* cold reset ENET1 MAC */
0107 #define AR5312_RESET_UART0      0x00000100  /* cold reset UART0 */
0108 #define AR5312_RESET_WLAN1      0x00000200  /* cold reset WLAN MAC/BB */
0109 #define AR5312_RESET_APB        0x00000400  /* cold reset APB ar5312 */
0110 #define AR5312_RESET_WARM_PROC      0x00001000  /* warm reset MIPS core */
0111 #define AR5312_RESET_WARM_WLAN0_MAC 0x00002000  /* warm reset WLAN0 MAC */
0112 #define AR5312_RESET_WARM_WLAN0_BB  0x00004000  /* warm reset WLAN0 BB */
0113 #define AR5312_RESET_NMI        0x00010000  /* send an NMI to the CPU */
0114 #define AR5312_RESET_WARM_WLAN1_MAC 0x00020000  /* warm reset WLAN1 MAC */
0115 #define AR5312_RESET_WARM_WLAN1_BB  0x00040000  /* warm reset WLAN1 BB */
0116 #define AR5312_RESET_LOCAL_BUS      0x00080000  /* reset local bus */
0117 #define AR5312_RESET_WDOG       0x00100000  /* last reset was a wdt */
0118
0119 #define AR5312_RESET_WMAC0_BITS     (AR5312_RESET_WLAN0 |\
0120                      AR5312_RESET_WARM_WLAN0_MAC |\
0121                      AR5312_RESET_WARM_WLAN0_BB)
0122
0123 #define AR5312_RESET_WMAC1_BITS     (AR5312_RESET_WLAN1 |\
0124                      AR5312_RESET_WARM_WLAN1_MAC |\
0125                      AR5312_RESET_WARM_WLAN1_BB)
0126
0127 /* AR5312_CLOCKCTL1 register bit field definitions */
0128 #define AR5312_CLOCKCTL1_PREDIVIDE_MASK     0x00000030
0129 #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT    4
0130 #define AR5312_CLOCKCTL1_MULTIPLIER_MASK    0x00001f00
0131 #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT   8
0132 #define AR5312_CLOCKCTL1_DOUBLER_MASK       0x00010000
0133
0134 /* Valid for AR5312 and AR2312 */
0135 #define AR5312_CLOCKCTL1_PREDIVIDE_MASK     0x00000030
0136 #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT    4
0137 #define AR5312_CLOCKCTL1_MULTIPLIER_MASK    0x00001f00
0138 #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT   8
0139 #define AR5312_CLOCKCTL1_DOUBLER_MASK       0x00010000
0140
0141 /* Valid for AR2313 */
0142 #define AR2313_CLOCKCTL1_PREDIVIDE_MASK     0x00003000
0143 #define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT    12
0144 #define AR2313_CLOCKCTL1_MULTIPLIER_MASK    0x001f0000
0145 #define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT   16
0146 #define AR2313_CLOCKCTL1_DOUBLER_MASK       0x00000000
0147
0148 /* AR5312_ENABLE register bit field definitions */
0149 #define AR5312_ENABLE_WLAN0         0x00000001
0150 #define AR5312_ENABLE_ENET0         0x00000002
0151 #define AR5312_ENABLE_ENET1         0x00000004
0152 #define AR5312_ENABLE_UART_AND_WLAN1_PIO    0x00000008/* UART & WLAN1 PIO */
0153 #define AR5312_ENABLE_WLAN1_DMA         0x00000010/* WLAN1 DMAs */
0154 #define AR5312_ENABLE_WLAN1     (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
0155                      AR5312_ENABLE_WLAN1_DMA)
0156
0157 /* AR5312_REV register bit field definitions */
0158 #define AR5312_REV_WMAC_MAJ 0x0000f000
0159 #define AR5312_REV_WMAC_MAJ_S   12
0160 #define AR5312_REV_WMAC_MIN 0x00000f00
0161 #define AR5312_REV_WMAC_MIN_S   8
0162 #define AR5312_REV_MAJ      0x000000f0
0163 #define AR5312_REV_MAJ_S    4
0164 #define AR5312_REV_MIN      0x0000000f
0165 #define AR5312_REV_MIN_S    0
0166 #define AR5312_REV_CHIP     (AR5312_REV_MAJ|AR5312_REV_MIN)
0167
0168 /* Major revision numbers, bits 7..4 of Revision ID register */
0169 #define AR5312_REV_MAJ_AR5312       0x4
0170 #define AR5312_REV_MAJ_AR2313       0x5
0171
0172 /* Minor revision numbers, bits 3..0 of Revision ID register */
0173 #define AR5312_REV_MIN_DUAL     0x0 /* Dual WLAN version */
0174 #define AR5312_REV_MIN_SINGLE       0x1 /* Single WLAN version */
0175
0176 /*
0177  * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
0178  */
0179 #define AR5312_FLASHCTL0    0x0000
0180 #define AR5312_FLASHCTL1    0x0004
0181 #define AR5312_FLASHCTL2    0x0008
0182
0183 /* AR5312_FLASHCTL register bit field definitions */
0184 #define AR5312_FLASHCTL_IDCY    0x0000000f  /* Idle cycle turnaround time */
0185 #define AR5312_FLASHCTL_IDCY_S  0
0186 #define AR5312_FLASHCTL_WST1    0x000003e0  /* Wait state 1 */
0187 #define AR5312_FLASHCTL_WST1_S  5
0188 #define AR5312_FLASHCTL_RBLE    0x00000400  /* Read byte lane enable */
0189 #define AR5312_FLASHCTL_WST2    0x0000f800  /* Wait state 2 */
0190 #define AR5312_FLASHCTL_WST2_S  11
0191 #define AR5312_FLASHCTL_AC  0x00070000  /* Flash addr check (added) */
0192 #define AR5312_FLASHCTL_AC_S    16
0193 #define AR5312_FLASHCTL_AC_128K 0x00000000
0194 #define AR5312_FLASHCTL_AC_256K 0x00010000
0195 #define AR5312_FLASHCTL_AC_512K 0x00020000
0196 #define AR5312_FLASHCTL_AC_1M   0x00030000
0197 #define AR5312_FLASHCTL_AC_2M   0x00040000
0198 #define AR5312_FLASHCTL_AC_4M   0x00050000
0199 #define AR5312_FLASHCTL_AC_8M   0x00060000
0200 #define AR5312_FLASHCTL_AC_RES  0x00070000  /* 16MB is not supported */
0201 #define AR5312_FLASHCTL_E   0x00080000  /* Flash bank enable (added) */
0202 #define AR5312_FLASHCTL_BUSERR  0x01000000  /* Bus transfer error flag */
0203 #define AR5312_FLASHCTL_WPERR   0x02000000  /* Write protect error flag */
0204 #define AR5312_FLASHCTL_WP  0x04000000  /* Write protect */
0205 #define AR5312_FLASHCTL_BM  0x08000000  /* Burst mode */
0206 #define AR5312_FLASHCTL_MW  0x30000000  /* Mem width */
0207 #define AR5312_FLASHCTL_MW8 0x00000000  /* Mem width x8 */
0208 #define AR5312_FLASHCTL_MW16    0x10000000  /* Mem width x16 */
0209 #define AR5312_FLASHCTL_MW32    0x20000000  /* Mem width x32 (not supp) */
0210 #define AR5312_FLASHCTL_ATNR    0x00000000  /* Access == no retry */
0211 #define AR5312_FLASHCTL_ATR 0x80000000  /* Access == retry every */
0212 #define AR5312_FLASHCTL_ATR4    0xc0000000  /* Access == retry every 4 */
0213
0214 /*
0215  * ARM SDRAM Controller -- just enough to determine memory size
0216  */
0217 #define AR5312_MEM_CFG1     0x0004
0218
0219 #define AR5312_MEM_CFG1_AC0_M   0x00000700  /* bank 0: SDRAM addr check */
0220 #define AR5312_MEM_CFG1_AC0_S   8
0221 #define AR5312_MEM_CFG1_AC1_M   0x00007000  /* bank 1: SDRAM addr check */
0222 #define AR5312_MEM_CFG1_AC1_S   12
0223
0224 #endif  /* __ASM_MACH_ATH25_AR5312_REGS_H */