mips/ath25/ar2315.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
0007  * Copyright (C) 2006 FON Technology, SL.
0008  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
0009  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
0010  * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
0011  */
0012
0013 /*
0014  * Platform devices for Atheros AR2315 SoCs
0015  */
0016
0017 #include <linux/init.h>
0018 #include <linux/kernel.h>
0019 #include <linux/bitops.h>
0020 #include <linux/irqdomain.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/memblock.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/reboot.h>
0025 #include <asm/bootinfo.h>
0026 #include <asm/reboot.h>
0027 #include <asm/time.h>
0028
0029 #include <ath25_platform.h>
0030
0031 #include "devices.h"
0032 #include "ar2315.h"
0033 #include "ar2315_regs.h"
0034
0035 static void __iomem *ar2315_rst_base;
0036 static struct irq_domain *ar2315_misc_irq_domain;
0037
0038 static inline u32 ar2315_rst_reg_read(u32 reg)
0039 {
0040     return __raw_readl(ar2315_rst_base + reg);
0041 }
0042
0043 static inline void ar2315_rst_reg_write(u32 reg, u32 val)
0044 {
0045     __raw_writel(val, ar2315_rst_base + reg);
0046 }
0047
0048 static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
0049 {
0050     u32 ret = ar2315_rst_reg_read(reg);
0051
0052     ret &= ~mask;
0053     ret |= val;
0054     ar2315_rst_reg_write(reg, ret);
0055 }
0056
0057 static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
0058 {
0059     ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
0060     ar2315_rst_reg_read(AR2315_AHB_ERR1);
0061
0062     pr_emerg("AHB fatal error\n");
0063     machine_restart("AHB error"); /* Catastrophic failure */
0064
0065     return IRQ_HANDLED;
0066 }
0067
0068 static void ar2315_misc_irq_handler(struct irq_desc *desc)
0069 {
0070     u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
0071               ar2315_rst_reg_read(AR2315_IMR);
0072     unsigned nr;
0073     int ret = 0;
0074
0075     if (pending) {
0076         struct irq_domain *domain = irq_desc_get_handler_data(desc);
0077
0078         nr = __ffs(pending);
0079
0080         if (nr == AR2315_MISC_IRQ_GPIO)
0081             ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
0082         else if (nr == AR2315_MISC_IRQ_WATCHDOG)
0083             ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
0084
0085         ret = generic_handle_domain_irq(domain, nr);
0086     }
0087
0088     if (!pending || ret)
0089         spurious_interrupt();
0090 }
0091
0092 static void ar2315_misc_irq_unmask(struct irq_data *d)
0093 {
0094     ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
0095 }
0096
0097 static void ar2315_misc_irq_mask(struct irq_data *d)
0098 {
0099     ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
0100 }
0101
0102 static struct irq_chip ar2315_misc_irq_chip = {
0103     .name       = "ar2315-misc",
0104     .irq_unmask = ar2315_misc_irq_unmask,
0105     .irq_mask   = ar2315_misc_irq_mask,
0106 };
0107
0108 static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
0109                    irq_hw_number_t hw)
0110 {
0111     irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
0112     return 0;
0113 }
0114
0115 static const struct irq_domain_ops ar2315_misc_irq_domain_ops = {
0116     .map = ar2315_misc_irq_map,
0117 };
0118
0119 /*
0120  * Called when an interrupt is received, this function
0121  * determines exactly which interrupt it was, and it
0122  * invokes the appropriate handler.
0123  *
0124  * Implicitly, we also define interrupt priority by
0125  * choosing which to dispatch first.
0126  */
0127 static void ar2315_irq_dispatch(void)
0128 {
0129     u32 pending = read_c0_status() & read_c0_cause();
0130
0131     if (pending & CAUSEF_IP3)
0132         do_IRQ(AR2315_IRQ_WLAN0);
0133 #ifdef CONFIG_PCI_AR2315
0134     else if (pending & CAUSEF_IP5)
0135         do_IRQ(AR2315_IRQ_LCBUS_PCI);
0136 #endif
0137     else if (pending & CAUSEF_IP2)
0138         do_IRQ(AR2315_IRQ_MISC);
0139     else if (pending & CAUSEF_IP7)
0140         do_IRQ(ATH25_IRQ_CPU_CLOCK);
0141     else
0142         spurious_interrupt();
0143 }
0144
0145 void __init ar2315_arch_init_irq(void)
0146 {
0147     struct irq_domain *domain;
0148     unsigned irq;
0149
0150     ath25_irq_dispatch = ar2315_irq_dispatch;
0151
0152     domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
0153                        &ar2315_misc_irq_domain_ops, NULL);
0154     if (!domain)
0155         panic("Failed to add IRQ domain");
0156
0157     irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
0158     if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
0159             NULL))
0160         pr_err("Failed to register ar2315-ahb-error interrupt\n");
0161
0162     irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
0163                      ar2315_misc_irq_handler, domain);
0164
0165     ar2315_misc_irq_domain = domain;
0166 }
0167
0168 void __init ar2315_init_devices(void)
0169 {
0170     /* Find board configuration */
0171     ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
0172
0173     ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
0174 }
0175
0176 static void ar2315_restart(char *command)
0177 {
0178     void (*mips_reset_vec)(void) = (void *)0xbfc00000;
0179
0180     local_irq_disable();
0181
0182     /* try reset the system via reset control */
0183     ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
0184
0185     /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
0186      * a workaround. Give it some time to attempt a gpio based hardware
0187      * reset (atheros reference design workaround) */
0188
0189     /* TODO: implement the GPIO reset workaround */
0190
0191     /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
0192      * workaround. Attempt to jump to the mips reset location -
0193      * the boot loader itself might be able to recover the system */
0194     mips_reset_vec();
0195 }
0196
0197 /*
0198  * This table is indexed by bits 5..4 of the CLOCKCTL1 register
0199  * to determine the predevisor value.
0200  */
0201 static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
0202 static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
0203
0204 static unsigned __init ar2315_sys_clk(u32 clock_ctl)
0205 {
0206     unsigned int pllc_ctrl, cpu_div;
0207     unsigned int pllc_out, refdiv, fdiv, divby2;
0208     unsigned int clk_div;
0209
0210     pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
0211     refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
0212     refdiv = clockctl1_predivide_table[refdiv];
0213     fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
0214     divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
0215     pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
0216
0217     /* clkm input selected */
0218     switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
0219     case 0:
0220     case 1:
0221         clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
0222         clk_div = pllc_divide_table[clk_div];
0223         break;
0224     case 2:
0225         clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
0226         clk_div = pllc_divide_table[clk_div];
0227         break;
0228     default:
0229         pllc_out = 40000000;
0230         clk_div = 1;
0231         break;
0232     }
0233
0234     cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
0235     cpu_div = cpu_div * 2 ?: 1;
0236
0237     return pllc_out / (clk_div * cpu_div);
0238 }
0239
0240 static inline unsigned ar2315_cpu_frequency(void)
0241 {
0242     return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
0243 }
0244
0245 static inline unsigned ar2315_apb_frequency(void)
0246 {
0247     return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
0248 }
0249
0250 void __init ar2315_plat_time_init(void)
0251 {
0252     mips_hpt_frequency = ar2315_cpu_frequency() / 2;
0253 }
0254
0255 void __init ar2315_plat_mem_setup(void)
0256 {
0257     void __iomem *sdram_base;
0258     u32 memsize, memcfg;
0259     u32 devid;
0260     u32 config;
0261
0262     /* Detect memory size */
0263     sdram_base = ioremap(AR2315_SDRAMCTL_BASE,
0264                      AR2315_SDRAMCTL_SIZE);
0265     memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
0266     memsize   = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
0267     memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
0268     memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
0269     memsize <<= 3;
0270     memblock_add(0, memsize);
0271     iounmap(sdram_base);
0272
0273     ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE);
0274
0275     /* Detect the hardware based on the device ID */
0276     devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
0277     switch (devid) {
0278     case 0x91:  /* Need to check */
0279         ath25_soc = ATH25_SOC_AR2318;
0280         break;
0281     case 0x90:
0282         ath25_soc = ATH25_SOC_AR2317;
0283         break;
0284     case 0x87:
0285         ath25_soc = ATH25_SOC_AR2316;
0286         break;
0287     case 0x86:
0288     default:
0289         ath25_soc = ATH25_SOC_AR2315;
0290         break;
0291     }
0292     ath25_board.devid = devid;
0293
0294     /* Clear any lingering AHB errors */
0295     config = read_c0_config();
0296     write_c0_config(config & ~0x3);
0297     ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
0298     ar2315_rst_reg_read(AR2315_AHB_ERR1);
0299     ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
0300
0301     _machine_restart = ar2315_restart;
0302 }
0303
0304 #ifdef CONFIG_PCI_AR2315
0305 static struct resource ar2315_pci_res[] = {
0306     {
0307         .name = "ar2315-pci-ctrl",
0308         .flags = IORESOURCE_MEM,
0309         .start = AR2315_PCI_BASE,
0310         .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
0311     },
0312     {
0313         .name = "ar2315-pci-ext",
0314         .flags = IORESOURCE_MEM,
0315         .start = AR2315_PCI_EXT_BASE,
0316         .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
0317     },
0318     {
0319         .name = "ar2315-pci",
0320         .flags = IORESOURCE_IRQ,
0321         .start = AR2315_IRQ_LCBUS_PCI,
0322         .end = AR2315_IRQ_LCBUS_PCI,
0323     },
0324 };
0325 #endif
0326
0327 void __init ar2315_arch_init(void)
0328 {
0329     unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
0330                       AR2315_MISC_IRQ_UART0);
0331
0332     ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
0333
0334 #ifdef CONFIG_PCI_AR2315
0335     if (ath25_soc == ATH25_SOC_AR2315) {
0336         /* Reset PCI DMA logic */
0337         ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
0338         msleep(20);
0339         ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
0340         msleep(20);
0341
0342         /* Configure endians */
0343         ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
0344                     AR2315_CONFIG_PCIAHB_BRIDGE);
0345
0346         /* Configure as PCI host with DMA */
0347         ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
0348                   (AR2315_PCICLK_IN_FREQ_DIV_6 <<
0349                    AR2315_PCICLK_DIV_S));
0350         ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
0351         ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
0352                     AR2315_IF_MASK, AR2315_IF_PCI |
0353                     AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
0354                     (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
0355                      AR2315_IF_PCI_CLK_SHIFT));
0356
0357         platform_device_register_simple("ar2315-pci", -1,
0358                         ar2315_pci_res,
0359                         ARRAY_SIZE(ar2315_pci_res));
0360     }
0361 #endif
0362 }