mips/ar7/irq.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
0005  */
0006
0007 #include <linux/interrupt.h>
0008 #include <linux/io.h>
0009 #include <linux/irq.h>
0010
0011 #include <asm/irq_cpu.h>
0012 #include <asm/mipsregs.h>
0013 #include <asm/mach-ar7/ar7.h>
0014
0015 #define EXCEPT_OFFSET   0x80
0016 #define PACE_OFFSET 0xA0
0017 #define CHNLS_OFFSET    0x200
0018
0019 #define REG_OFFSET(irq, reg)    ((irq) / 32 * 0x4 + reg * 0x10)
0020 #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
0021 #define SEC_SR_OFFSET       (SEC_REG_OFFSET(0)) /* 0x80 */
0022 #define CR_OFFSET(irq)      (REG_OFFSET(irq, 1))    /* 0x10 */
0023 #define SEC_CR_OFFSET       (SEC_REG_OFFSET(1)) /* 0x88 */
0024 #define ESR_OFFSET(irq)     (REG_OFFSET(irq, 2))    /* 0x20 */
0025 #define SEC_ESR_OFFSET      (SEC_REG_OFFSET(2)) /* 0x90 */
0026 #define ECR_OFFSET(irq)     (REG_OFFSET(irq, 3))    /* 0x30 */
0027 #define SEC_ECR_OFFSET      (SEC_REG_OFFSET(3)) /* 0x98 */
0028 #define PIR_OFFSET      (0x40)
0029 #define MSR_OFFSET      (0x44)
0030 #define PM_OFFSET(irq)      (REG_OFFSET(irq, 5))    /* 0x50 */
0031 #define TM_OFFSET(irq)      (REG_OFFSET(irq, 6))    /* 0x60 */
0032
0033 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
0034
0035 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
0036
0037 static int ar7_irq_base;
0038
0039 static void ar7_unmask_irq(struct irq_data *d)
0040 {
0041     writel(1 << ((d->irq - ar7_irq_base) % 32),
0042            REG(ESR_OFFSET(d->irq - ar7_irq_base)));
0043 }
0044
0045 static void ar7_mask_irq(struct irq_data *d)
0046 {
0047     writel(1 << ((d->irq - ar7_irq_base) % 32),
0048            REG(ECR_OFFSET(d->irq - ar7_irq_base)));
0049 }
0050
0051 static void ar7_ack_irq(struct irq_data *d)
0052 {
0053     writel(1 << ((d->irq - ar7_irq_base) % 32),
0054            REG(CR_OFFSET(d->irq - ar7_irq_base)));
0055 }
0056
0057 static void ar7_unmask_sec_irq(struct irq_data *d)
0058 {
0059     writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
0060 }
0061
0062 static void ar7_mask_sec_irq(struct irq_data *d)
0063 {
0064     writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
0065 }
0066
0067 static void ar7_ack_sec_irq(struct irq_data *d)
0068 {
0069     writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
0070 }
0071
0072 static struct irq_chip ar7_irq_type = {
0073     .name = "AR7",
0074     .irq_unmask = ar7_unmask_irq,
0075     .irq_mask = ar7_mask_irq,
0076     .irq_ack = ar7_ack_irq
0077 };
0078
0079 static struct irq_chip ar7_sec_irq_type = {
0080     .name = "AR7",
0081     .irq_unmask = ar7_unmask_sec_irq,
0082     .irq_mask = ar7_mask_sec_irq,
0083     .irq_ack = ar7_ack_sec_irq,
0084 };
0085
0086 static void __init ar7_irq_init(int base)
0087 {
0088     int i;
0089     /*
0090      * Disable interrupts and clear pending
0091      */
0092     writel(0xffffffff, REG(ECR_OFFSET(0)));
0093     writel(0xff, REG(ECR_OFFSET(32)));
0094     writel(0xffffffff, REG(SEC_ECR_OFFSET));
0095     writel(0xffffffff, REG(CR_OFFSET(0)));
0096     writel(0xff, REG(CR_OFFSET(32)));
0097     writel(0xffffffff, REG(SEC_CR_OFFSET));
0098
0099     ar7_irq_base = base;
0100
0101     for (i = 0; i < 40; i++) {
0102         writel(i, REG(CHNL_OFFSET(i)));
0103         /* Primary IRQ's */
0104         irq_set_chip_and_handler(base + i, &ar7_irq_type,
0105                      handle_level_irq);
0106         /* Secondary IRQ's */
0107         if (i < 32)
0108             irq_set_chip_and_handler(base + i + 40,
0109                          &ar7_sec_irq_type,
0110                          handle_level_irq);
0111     }
0112
0113     if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
0114             NULL))
0115         pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
0116     if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
0117             "AR7 cascade interrupt", NULL)) {
0118         pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
0119                ar7_irq_base);
0120     }
0121     set_c0_status(IE_IRQ0);
0122 }
0123
0124 void __init arch_init_irq(void)
0125 {
0126     mips_cpu_irq_init();
0127     ar7_irq_init(8);
0128 }
0129
0130 static void ar7_cascade(void)
0131 {
0132     u32 status;
0133     int i, irq;
0134
0135     /* Primary IRQ's */
0136     irq = readl(REG(PIR_OFFSET)) & 0x3f;
0137     if (irq) {
0138         do_IRQ(ar7_irq_base + irq);
0139         return;
0140     }
0141
0142     /* Secondary IRQ's are cascaded through primary '0' */
0143     writel(1, REG(CR_OFFSET(irq)));
0144     status = readl(REG(SEC_SR_OFFSET));
0145     for (i = 0; i < 32; i++) {
0146         if (status & 1) {
0147             do_IRQ(ar7_irq_base + i + 40);
0148             return;
0149         }
0150         status >>= 1;
0151     }
0152
0153     spurious_interrupt();
0154 }
0155
0156 asmlinkage void plat_irq_dispatch(void)
0157 {
0158     unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
0159     if (pending & STATUSF_IP7)      /* cpu timer */
0160         do_IRQ(7);
0161     else if (pending & STATUSF_IP2)     /* int0 hardware line */
0162         ar7_cascade();
0163     else
0164         spurious_interrupt();
0165 }