mips/ar7/clock.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
0005  * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010 #include <linux/types.h>
0011 #include <linux/export.h>
0012 #include <linux/delay.h>
0013 #include <linux/gcd.h>
0014 #include <linux/io.h>
0015 #include <linux/err.h>
0016 #include <linux/clkdev.h>
0017 #include <linux/clk.h>
0018 #include <linux/clk-provider.h>
0019
0020 #include <asm/addrspace.h>
0021 #include <asm/mach-ar7/ar7.h>
0022
0023 #define BOOT_PLL_SOURCE_MASK    0x3
0024 #define CPU_PLL_SOURCE_SHIFT    16
0025 #define BUS_PLL_SOURCE_SHIFT    14
0026 #define USB_PLL_SOURCE_SHIFT    18
0027 #define DSP_PLL_SOURCE_SHIFT    22
0028 #define BOOT_PLL_SOURCE_AFE 0
0029 #define BOOT_PLL_SOURCE_BUS 0
0030 #define BOOT_PLL_SOURCE_REF 1
0031 #define BOOT_PLL_SOURCE_XTAL    2
0032 #define BOOT_PLL_SOURCE_CPU 3
0033 #define BOOT_PLL_BYPASS     0x00000020
0034 #define BOOT_PLL_ASYNC_MODE 0x02000000
0035 #define BOOT_PLL_2TO1_MODE  0x00008000
0036
0037 #define TNETD7200_CLOCK_ID_CPU  0
0038 #define TNETD7200_CLOCK_ID_DSP  1
0039 #define TNETD7200_CLOCK_ID_USB  2
0040
0041 #define TNETD7200_DEF_CPU_CLK   211000000
0042 #define TNETD7200_DEF_DSP_CLK   125000000
0043 #define TNETD7200_DEF_USB_CLK   48000000
0044
0045 struct tnetd7300_clock {
0046     u32 ctrl;
0047 #define PREDIV_MASK 0x001f0000
0048 #define PREDIV_SHIFT    16
0049 #define POSTDIV_MASK    0x0000001f
0050     u32 unused1[3];
0051     u32 pll;
0052 #define MUL_MASK    0x0000f000
0053 #define MUL_SHIFT   12
0054 #define PLL_MODE_MASK   0x00000001
0055 #define PLL_NDIV    0x00000800
0056 #define PLL_DIV     0x00000002
0057 #define PLL_STATUS  0x00000001
0058     u32 unused2[3];
0059 };
0060
0061 struct tnetd7300_clocks {
0062     struct tnetd7300_clock bus;
0063     struct tnetd7300_clock cpu;
0064     struct tnetd7300_clock usb;
0065     struct tnetd7300_clock dsp;
0066 };
0067
0068 struct tnetd7200_clock {
0069     u32 ctrl;
0070     u32 unused1[3];
0071 #define DIVISOR_ENABLE_MASK 0x00008000
0072     u32 mul;
0073     u32 prediv;
0074     u32 postdiv;
0075     u32 postdiv2;
0076     u32 unused2[6];
0077     u32 cmd;
0078     u32 status;
0079     u32 cmden;
0080     u32 padding[15];
0081 };
0082
0083 struct tnetd7200_clocks {
0084     struct tnetd7200_clock cpu;
0085     struct tnetd7200_clock dsp;
0086     struct tnetd7200_clock usb;
0087 };
0088
0089 struct clk_rate {
0090     u32 rate;
0091 };
0092 static struct clk_rate bus_clk = {
0093     .rate   = 125000000,
0094 };
0095
0096 static struct clk_rate cpu_clk = {
0097     .rate   = 150000000,
0098 };
0099
0100 static void approximate(int base, int target, int *prediv,
0101             int *postdiv, int *mul)
0102 {
0103     int i, j, k, freq, res = target;
0104     for (i = 1; i <= 16; i++)
0105         for (j = 1; j <= 32; j++)
0106             for (k = 1; k <= 32; k++) {
0107                 freq = abs(base / j * i / k - target);
0108                 if (freq < res) {
0109                     res = freq;
0110                     *mul = i;
0111                     *prediv = j;
0112                     *postdiv = k;
0113                 }
0114             }
0115 }
0116
0117 static void calculate(int base, int target, int *prediv, int *postdiv,
0118     int *mul)
0119 {
0120     int tmp_gcd, tmp_base, tmp_freq;
0121
0122     for (*prediv = 1; *prediv <= 32; (*prediv)++) {
0123         tmp_base = base / *prediv;
0124         tmp_gcd = gcd(target, tmp_base);
0125         *mul = target / tmp_gcd;
0126         *postdiv = tmp_base / tmp_gcd;
0127         if ((*mul < 1) || (*mul >= 16))
0128             continue;
0129         if ((*postdiv > 0) & (*postdiv <= 32))
0130             break;
0131     }
0132
0133     if (base / *prediv * *mul / *postdiv != target) {
0134         approximate(base, target, prediv, postdiv, mul);
0135         tmp_freq = base / *prediv * *mul / *postdiv;
0136         printk(KERN_WARNING
0137                "Adjusted requested frequency %d to %d\n",
0138                target, tmp_freq);
0139     }
0140
0141     printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
0142            *prediv, *postdiv, *mul);
0143 }
0144
0145 static int tnetd7300_dsp_clock(void)
0146 {
0147     u32 didr1, didr2;
0148     u8 rev = ar7_chip_rev();
0149     didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
0150     didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
0151     if (didr2 & (1 << 23))
0152         return 0;
0153     if ((rev >= 0x23) && (rev != 0x57))
0154         return 250000000;
0155     if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
0156         > 4208000)
0157         return 250000000;
0158     return 0;
0159 }
0160
0161 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
0162     u32 *bootcr, u32 bus_clock)
0163 {
0164     int product;
0165     int base_clock = AR7_REF_CLOCK;
0166     u32 ctrl = readl(&clock->ctrl);
0167     u32 pll = readl(&clock->pll);
0168     int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
0169     int postdiv = (ctrl & POSTDIV_MASK) + 1;
0170     int divisor = prediv * postdiv;
0171     int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
0172
0173     switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
0174     case BOOT_PLL_SOURCE_BUS:
0175         base_clock = bus_clock;
0176         break;
0177     case BOOT_PLL_SOURCE_REF:
0178         base_clock = AR7_REF_CLOCK;
0179         break;
0180     case BOOT_PLL_SOURCE_XTAL:
0181         base_clock = AR7_XTAL_CLOCK;
0182         break;
0183     case BOOT_PLL_SOURCE_CPU:
0184         base_clock = cpu_clk.rate;
0185         break;
0186     }
0187
0188     if (*bootcr & BOOT_PLL_BYPASS)
0189         return base_clock / divisor;
0190
0191     if ((pll & PLL_MODE_MASK) == 0)
0192         return (base_clock >> (mul / 16 + 1)) / divisor;
0193
0194     if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
0195         product = (mul & 1) ?
0196             (base_clock * mul) >> 1 :
0197             (base_clock * (mul - 1)) >> 2;
0198         return product / divisor;
0199     }
0200
0201     if (mul == 16)
0202         return base_clock / divisor;
0203
0204     return base_clock * mul / divisor;
0205 }
0206
0207 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
0208     u32 *bootcr, u32 frequency)
0209 {
0210     int prediv, postdiv, mul;
0211     int base_clock = bus_clk.rate;
0212
0213     switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
0214     case BOOT_PLL_SOURCE_BUS:
0215         base_clock = bus_clk.rate;
0216         break;
0217     case BOOT_PLL_SOURCE_REF:
0218         base_clock = AR7_REF_CLOCK;
0219         break;
0220     case BOOT_PLL_SOURCE_XTAL:
0221         base_clock = AR7_XTAL_CLOCK;
0222         break;
0223     case BOOT_PLL_SOURCE_CPU:
0224         base_clock = cpu_clk.rate;
0225         break;
0226     }
0227
0228     calculate(base_clock, frequency, &prediv, &postdiv, &mul);
0229
0230     writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
0231     mdelay(1);
0232     writel(4, &clock->pll);
0233     while (readl(&clock->pll) & PLL_STATUS)
0234         ;
0235     writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
0236     mdelay(75);
0237 }
0238
0239 static void __init tnetd7300_init_clocks(void)
0240 {
0241     u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
0242     struct tnetd7300_clocks *clocks =
0243                     ioremap(UR8_REGS_CLOCKS,
0244                     sizeof(struct tnetd7300_clocks));
0245     u32 dsp_clk;
0246     struct clk *clk;
0247
0248     bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
0249         &clocks->bus, bootcr, AR7_AFE_CLOCK);
0250
0251     if (*bootcr & BOOT_PLL_ASYNC_MODE)
0252         cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
0253             &clocks->cpu, bootcr, AR7_AFE_CLOCK);
0254     else
0255         cpu_clk.rate = bus_clk.rate;
0256
0257     dsp_clk = tnetd7300_dsp_clock();
0258     if (dsp_clk == 250000000)
0259         tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
0260             bootcr, dsp_clk);
0261
0262     iounmap(clocks);
0263     iounmap(bootcr);
0264
0265     clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
0266     clkdev_create(clk, "cpu", NULL);
0267     clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk);
0268     clkdev_create(clk, "dsp", NULL);
0269 }
0270
0271 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
0272     int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
0273 {
0274     printk(KERN_INFO
0275         "Clocks: base = %d, frequency = %u, prediv = %d, "
0276         "postdiv = %d, postdiv2 = %d, mul = %d\n",
0277         base, frequency, prediv, postdiv, postdiv2, mul);
0278
0279     writel(0, &clock->ctrl);
0280     writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
0281     writel((mul - 1) & 0xF, &clock->mul);
0282
0283     while (readl(&clock->status) & 0x1)
0284         ; /* nop */
0285
0286     writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
0287
0288     writel(readl(&clock->cmden) | 1, &clock->cmden);
0289     writel(readl(&clock->cmd) | 1, &clock->cmd);
0290
0291     while (readl(&clock->status) & 0x1)
0292         ; /* nop */
0293
0294     writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
0295
0296     writel(readl(&clock->cmden) | 1, &clock->cmden);
0297     writel(readl(&clock->cmd) | 1, &clock->cmd);
0298
0299     while (readl(&clock->status) & 0x1)
0300         ; /* nop */
0301
0302     writel(readl(&clock->ctrl) | 1, &clock->ctrl);
0303 }
0304
0305 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
0306 {
0307     if (*bootcr & BOOT_PLL_ASYNC_MODE)
0308         /* Async */
0309         switch (clock_id) {
0310         case TNETD7200_CLOCK_ID_DSP:
0311             return AR7_REF_CLOCK;
0312         default:
0313             return AR7_AFE_CLOCK;
0314         }
0315     else
0316         /* Sync */
0317         if (*bootcr & BOOT_PLL_2TO1_MODE)
0318             /* 2:1 */
0319             switch (clock_id) {
0320             case TNETD7200_CLOCK_ID_DSP:
0321                 return AR7_REF_CLOCK;
0322             default:
0323                 return AR7_AFE_CLOCK;
0324             }
0325         else
0326             /* 1:1 */
0327             return AR7_REF_CLOCK;
0328 }
0329
0330
0331 static void __init tnetd7200_init_clocks(void)
0332 {
0333     u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
0334     struct tnetd7200_clocks *clocks =
0335                     ioremap(AR7_REGS_CLOCKS,
0336                     sizeof(struct tnetd7200_clocks));
0337     int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
0338     int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
0339     int usb_base, usb_mul, usb_prediv, usb_postdiv;
0340     struct clk *clk;
0341
0342     cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
0343     dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
0344
0345     if (*bootcr & BOOT_PLL_ASYNC_MODE) {
0346         printk(KERN_INFO "Clocks: Async mode\n");
0347
0348         printk(KERN_INFO "Clocks: Setting DSP clock\n");
0349         calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
0350             &dsp_prediv, &dsp_postdiv, &dsp_mul);
0351         bus_clk.rate =
0352             ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
0353         tnetd7200_set_clock(dsp_base, &clocks->dsp,
0354             dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
0355             bus_clk.rate);
0356
0357         printk(KERN_INFO "Clocks: Setting CPU clock\n");
0358         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
0359             &cpu_postdiv, &cpu_mul);
0360         cpu_clk.rate =
0361             ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
0362         tnetd7200_set_clock(cpu_base, &clocks->cpu,
0363             cpu_prediv, cpu_postdiv, -1, cpu_mul,
0364             cpu_clk.rate);
0365
0366     } else
0367         if (*bootcr & BOOT_PLL_2TO1_MODE) {
0368             printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
0369
0370             printk(KERN_INFO "Clocks: Setting CPU clock\n");
0371             calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
0372                 &cpu_postdiv, &cpu_mul);
0373             cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
0374                                 / cpu_postdiv;
0375             tnetd7200_set_clock(cpu_base, &clocks->cpu,
0376                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
0377                 cpu_clk.rate);
0378
0379             printk(KERN_INFO "Clocks: Setting DSP clock\n");
0380             calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
0381                 &dsp_postdiv, &dsp_mul);
0382             bus_clk.rate = cpu_clk.rate / 2;
0383             tnetd7200_set_clock(dsp_base, &clocks->dsp,
0384                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
0385                 dsp_mul * 2, bus_clk.rate);
0386         } else {
0387             printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
0388
0389             printk(KERN_INFO "Clocks: Setting DSP clock\n");
0390             calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
0391                 &dsp_postdiv, &dsp_mul);
0392             bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
0393                                 / dsp_postdiv;
0394             tnetd7200_set_clock(dsp_base, &clocks->dsp,
0395                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
0396                 dsp_mul * 2, bus_clk.rate);
0397
0398             cpu_clk.rate = bus_clk.rate;
0399         }
0400
0401     printk(KERN_INFO "Clocks: Setting USB clock\n");
0402     usb_base = bus_clk.rate;
0403     calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
0404         &usb_postdiv, &usb_mul);
0405     tnetd7200_set_clock(usb_base, &clocks->usb,
0406         usb_prediv, usb_postdiv, -1, usb_mul,
0407         TNETD7200_DEF_USB_CLK);
0408
0409     iounmap(clocks);
0410     iounmap(bootcr);
0411
0412     clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
0413     clkdev_create(clk, "cpu", NULL);
0414     clkdev_create(clk, "dsp", NULL);
0415 }
0416
0417 void __init ar7_init_clocks(void)
0418 {
0419     struct clk *clk;
0420
0421     switch (ar7_chip_id()) {
0422     case AR7_CHIP_7100:
0423     case AR7_CHIP_7200:
0424         tnetd7200_init_clocks();
0425         break;
0426     case AR7_CHIP_7300:
0427         tnetd7300_init_clocks();
0428         break;
0429     default:
0430         break;
0431     }
0432     clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate);
0433     clkdev_create(clk, "bus", NULL);
0434     /* adjust vbus clock rate */
0435     clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2);
0436     clkdev_create(clk, "vbus", NULL);
0437     clkdev_create(clk, "cpmac", "cpmac.1");
0438     clkdev_create(clk, "cpmac", "cpmac.1");
0439 }