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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Alchemy Db1550/Pb1550 board support
0004  *
0005  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/gpio.h>
0011 #include <linux/i2c.h>
0012 #include <linux/init.h>
0013 #include <linux/io.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/mtd/mtd.h>
0016 #include <linux/mtd/platnand.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/spi/flash.h>
0021 #include <asm/bootinfo.h>
0022 #include <asm/mach-au1x00/au1000.h>
0023 #include <asm/mach-au1x00/gpio-au1000.h>
0024 #include <asm/mach-au1x00/au1xxx_eth.h>
0025 #include <asm/mach-au1x00/au1xxx_dbdma.h>
0026 #include <asm/mach-au1x00/au1xxx_psc.h>
0027 #include <asm/mach-au1x00/au1550_spi.h>
0028 #include <asm/mach-au1x00/au1550nd.h>
0029 #include <asm/mach-db1x00/bcsr.h>
0030 #include <prom.h>
0031 #include "platform.h"
0032 
0033 static void __init db1550_hw_setup(void)
0034 {
0035     void __iomem *base;
0036     unsigned long v;
0037 
0038     /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
0039      * as well as PSC1_SYNC for AC97 on PB1550.
0040      */
0041     v = alchemy_rdsys(AU1000_SYS_PINFUNC);
0042     alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
0043 
0044     /* reset the AC97 codec now, the reset time in the psc-ac97 driver
0045      * is apparently too short although it's ridiculous as it is.
0046      */
0047     base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
0048     __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
0049              base + PSC_SEL_OFFSET);
0050     __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
0051     wmb();
0052     __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
0053     wmb();
0054 }
0055 
0056 int __init db1550_board_setup(void)
0057 {
0058     unsigned short whoami;
0059 
0060     bcsr_init(DB1550_BCSR_PHYS_ADDR,
0061           DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
0062 
0063     whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
0064     switch (BCSR_WHOAMI_BOARD(whoami)) {
0065     case BCSR_WHOAMI_PB1550_SDR:
0066     case BCSR_WHOAMI_PB1550_DDR:
0067         bcsr_init(PB1550_BCSR_PHYS_ADDR,
0068               PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
0069         break;
0070     case BCSR_WHOAMI_DB1550:
0071         break;
0072     default:
0073         return -ENODEV;
0074     }
0075 
0076     pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d  "   \
0077         "Daughtercard ID %d\n", get_system_type(),
0078         (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
0079 
0080     db1550_hw_setup();
0081     return 0;
0082 }
0083 
0084 /*****************************************************************************/
0085 
0086 static u64 au1550_all_dmamask = DMA_BIT_MASK(32);
0087 
0088 static struct mtd_partition db1550_spiflash_parts[] = {
0089     {
0090         .name   = "spi_flash",
0091         .offset = 0,
0092         .size   = MTDPART_SIZ_FULL,
0093     },
0094 };
0095 
0096 static struct flash_platform_data db1550_spiflash_data = {
0097     .name       = "s25fl010",
0098     .parts      = db1550_spiflash_parts,
0099     .nr_parts   = ARRAY_SIZE(db1550_spiflash_parts),
0100     .type       = "m25p10",
0101 };
0102 
0103 static struct spi_board_info db1550_spi_devs[] __initdata = {
0104     {
0105         /* TI TMP121AIDBVR temp sensor */
0106         .modalias   = "tmp121",
0107         .max_speed_hz   = 2400000,
0108         .bus_num    = 0,
0109         .chip_select    = 0,
0110         .mode       = SPI_MODE_0,
0111     },
0112     {
0113         /* Spansion S25FL001D0FMA SPI flash */
0114         .modalias   = "m25p80",
0115         .max_speed_hz   = 2400000,
0116         .bus_num    = 0,
0117         .chip_select    = 1,
0118         .mode       = SPI_MODE_0,
0119         .platform_data  = &db1550_spiflash_data,
0120     },
0121 };
0122 
0123 static struct i2c_board_info db1550_i2c_devs[] __initdata = {
0124     { I2C_BOARD_INFO("24c04",  0x52),}, /* AT24C04-10 I2C eeprom */
0125     { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
0126     { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
0127 };
0128 
0129 /**********************************************************************/
0130 
0131 static void au1550_nand_cmd_ctrl(struct nand_chip *this, int cmd,
0132                  unsigned int ctrl)
0133 {
0134     unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
0135 
0136     ioaddr &= 0xffffff00;
0137 
0138     if (ctrl & NAND_CLE) {
0139         ioaddr += MEM_STNAND_CMD;
0140     } else if (ctrl & NAND_ALE) {
0141         ioaddr += MEM_STNAND_ADDR;
0142     } else {
0143         /* assume we want to r/w real data  by default */
0144         ioaddr += MEM_STNAND_DATA;
0145     }
0146     this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
0147     if (cmd != NAND_CMD_NONE) {
0148         __raw_writeb(cmd, this->legacy.IO_ADDR_W);
0149         wmb();
0150     }
0151 }
0152 
0153 static int au1550_nand_device_ready(struct nand_chip *this)
0154 {
0155     return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
0156 }
0157 
0158 static struct mtd_partition db1550_nand_parts[] = {
0159     {
0160         .name   = "NAND FS 0",
0161         .offset = 0,
0162         .size   = 8 * 1024 * 1024,
0163     },
0164     {
0165         .name   = "NAND FS 1",
0166         .offset = MTDPART_OFS_APPEND,
0167         .size   = MTDPART_SIZ_FULL
0168     },
0169 };
0170 
0171 struct platform_nand_data db1550_nand_platdata = {
0172     .chip = {
0173         .nr_chips   = 1,
0174         .chip_offset    = 0,
0175         .nr_partitions  = ARRAY_SIZE(db1550_nand_parts),
0176         .partitions = db1550_nand_parts,
0177         .chip_delay = 20,
0178     },
0179     .ctrl = {
0180         .dev_ready  = au1550_nand_device_ready,
0181         .cmd_ctrl   = au1550_nand_cmd_ctrl,
0182     },
0183 };
0184 
0185 static struct resource db1550_nand_res[] = {
0186     [0] = {
0187         .start  = 0x20000000,
0188         .end    = 0x200000ff,
0189         .flags  = IORESOURCE_MEM,
0190     },
0191 };
0192 
0193 static struct platform_device db1550_nand_dev = {
0194     .name       = "gen_nand",
0195     .num_resources  = ARRAY_SIZE(db1550_nand_res),
0196     .resource   = db1550_nand_res,
0197     .id     = -1,
0198     .dev        = {
0199         .platform_data = &db1550_nand_platdata,
0200     }
0201 };
0202 
0203 static struct au1550nd_platdata pb1550_nand_pd = {
0204     .parts      = db1550_nand_parts,
0205     .num_parts  = ARRAY_SIZE(db1550_nand_parts),
0206     .devwidth   = 0,    /* x8 NAND default, needs fixing up */
0207 };
0208 
0209 static struct platform_device pb1550_nand_dev = {
0210     .name       = "au1550-nand",
0211     .id     = -1,
0212     .resource   = db1550_nand_res,
0213     .num_resources  = ARRAY_SIZE(db1550_nand_res),
0214     .dev        = {
0215         .platform_data  = &pb1550_nand_pd,
0216     },
0217 };
0218 
0219 static void __init pb1550_nand_setup(void)
0220 {
0221     int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
0222                 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
0223 
0224     gpio_direction_input(206);  /* de-assert NAND CS# */
0225     switch (boot_swapboot) {
0226     case 0: case 2: case 8: case 0xC: case 0xD:
0227         /* x16 NAND Flash */
0228         pb1550_nand_pd.devwidth = 1;
0229         fallthrough;
0230     case 1: case 3: case 9: case 0xE: case 0xF:
0231         /* x8 NAND, already set up */
0232         platform_device_register(&pb1550_nand_dev);
0233     }
0234 }
0235 
0236 /**********************************************************************/
0237 
0238 static struct resource au1550_psc0_res[] = {
0239     [0] = {
0240         .start  = AU1550_PSC0_PHYS_ADDR,
0241         .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
0242         .flags  = IORESOURCE_MEM,
0243     },
0244     [1] = {
0245         .start  = AU1550_PSC0_INT,
0246         .end    = AU1550_PSC0_INT,
0247         .flags  = IORESOURCE_IRQ,
0248     },
0249     [2] = {
0250         .start  = AU1550_DSCR_CMD0_PSC0_TX,
0251         .end    = AU1550_DSCR_CMD0_PSC0_TX,
0252         .flags  = IORESOURCE_DMA,
0253     },
0254     [3] = {
0255         .start  = AU1550_DSCR_CMD0_PSC0_RX,
0256         .end    = AU1550_DSCR_CMD0_PSC0_RX,
0257         .flags  = IORESOURCE_DMA,
0258     },
0259 };
0260 
0261 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
0262 {
0263     if (cs)
0264         bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
0265     else
0266         bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
0267 }
0268 
0269 static struct au1550_spi_info db1550_spi_platdata = {
0270     .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
0271     .num_chipselect = 2,
0272     .activate_cs    = db1550_spi_cs_en,
0273 };
0274 
0275 
0276 static struct platform_device db1550_spi_dev = {
0277     .dev    = {
0278         .dma_mask       = &au1550_all_dmamask,
0279         .coherent_dma_mask  = DMA_BIT_MASK(32),
0280         .platform_data      = &db1550_spi_platdata,
0281     },
0282     .name       = "au1550-spi",
0283     .id     = 0,    /* bus number */
0284     .num_resources  = ARRAY_SIZE(au1550_psc0_res),
0285     .resource   = au1550_psc0_res,
0286 };
0287 
0288 /**********************************************************************/
0289 
0290 static struct resource au1550_psc1_res[] = {
0291     [0] = {
0292         .start  = AU1550_PSC1_PHYS_ADDR,
0293         .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
0294         .flags  = IORESOURCE_MEM,
0295     },
0296     [1] = {
0297         .start  = AU1550_PSC1_INT,
0298         .end    = AU1550_PSC1_INT,
0299         .flags  = IORESOURCE_IRQ,
0300     },
0301     [2] = {
0302         .start  = AU1550_DSCR_CMD0_PSC1_TX,
0303         .end    = AU1550_DSCR_CMD0_PSC1_TX,
0304         .flags  = IORESOURCE_DMA,
0305     },
0306     [3] = {
0307         .start  = AU1550_DSCR_CMD0_PSC1_RX,
0308         .end    = AU1550_DSCR_CMD0_PSC1_RX,
0309         .flags  = IORESOURCE_DMA,
0310     },
0311 };
0312 
0313 static struct platform_device db1550_ac97_dev = {
0314     .name       = "au1xpsc_ac97",
0315     .id     = 1,    /* PSC ID */
0316     .num_resources  = ARRAY_SIZE(au1550_psc1_res),
0317     .resource   = au1550_psc1_res,
0318 };
0319 
0320 
0321 static struct resource au1550_psc2_res[] = {
0322     [0] = {
0323         .start  = AU1550_PSC2_PHYS_ADDR,
0324         .end    = AU1550_PSC2_PHYS_ADDR + 0xfff,
0325         .flags  = IORESOURCE_MEM,
0326     },
0327     [1] = {
0328         .start  = AU1550_PSC2_INT,
0329         .end    = AU1550_PSC2_INT,
0330         .flags  = IORESOURCE_IRQ,
0331     },
0332     [2] = {
0333         .start  = AU1550_DSCR_CMD0_PSC2_TX,
0334         .end    = AU1550_DSCR_CMD0_PSC2_TX,
0335         .flags  = IORESOURCE_DMA,
0336     },
0337     [3] = {
0338         .start  = AU1550_DSCR_CMD0_PSC2_RX,
0339         .end    = AU1550_DSCR_CMD0_PSC2_RX,
0340         .flags  = IORESOURCE_DMA,
0341     },
0342 };
0343 
0344 static struct platform_device db1550_i2c_dev = {
0345     .name       = "au1xpsc_smbus",
0346     .id     = 0,    /* bus number */
0347     .num_resources  = ARRAY_SIZE(au1550_psc2_res),
0348     .resource   = au1550_psc2_res,
0349 };
0350 
0351 /**********************************************************************/
0352 
0353 static struct resource au1550_psc3_res[] = {
0354     [0] = {
0355         .start  = AU1550_PSC3_PHYS_ADDR,
0356         .end    = AU1550_PSC3_PHYS_ADDR + 0xfff,
0357         .flags  = IORESOURCE_MEM,
0358     },
0359     [1] = {
0360         .start  = AU1550_PSC3_INT,
0361         .end    = AU1550_PSC3_INT,
0362         .flags  = IORESOURCE_IRQ,
0363     },
0364     [2] = {
0365         .start  = AU1550_DSCR_CMD0_PSC3_TX,
0366         .end    = AU1550_DSCR_CMD0_PSC3_TX,
0367         .flags  = IORESOURCE_DMA,
0368     },
0369     [3] = {
0370         .start  = AU1550_DSCR_CMD0_PSC3_RX,
0371         .end    = AU1550_DSCR_CMD0_PSC3_RX,
0372         .flags  = IORESOURCE_DMA,
0373     },
0374 };
0375 
0376 static struct platform_device db1550_i2s_dev = {
0377     .name       = "au1xpsc_i2s",
0378     .id     = 3,    /* PSC ID */
0379     .num_resources  = ARRAY_SIZE(au1550_psc3_res),
0380     .resource   = au1550_psc3_res,
0381 };
0382 
0383 /**********************************************************************/
0384 
0385 static struct platform_device db1550_stac_dev = {
0386     .name       = "ac97-codec",
0387     .id     = 1,    /* on PSC1 */
0388 };
0389 
0390 static struct platform_device db1550_ac97dma_dev = {
0391     .name       = "au1xpsc-pcm",
0392     .id     = 1,    /* on PSC3 */
0393 };
0394 
0395 static struct platform_device db1550_i2sdma_dev = {
0396     .name       = "au1xpsc-pcm",
0397     .id     = 3,    /* on PSC3 */
0398 };
0399 
0400 static struct platform_device db1550_sndac97_dev = {
0401     .name       = "db1550-ac97",
0402     .dev = {
0403         .dma_mask       = &au1550_all_dmamask,
0404         .coherent_dma_mask  = DMA_BIT_MASK(32),
0405     },
0406 };
0407 
0408 static struct platform_device db1550_sndi2s_dev = {
0409     .name       = "db1550-i2s",
0410     .dev = {
0411         .dma_mask       = &au1550_all_dmamask,
0412         .coherent_dma_mask  = DMA_BIT_MASK(32),
0413     },
0414 };
0415 
0416 /**********************************************************************/
0417 
0418 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
0419 {
0420     if ((slot < 11) || (slot > 13) || pin == 0)
0421         return -1;
0422     if (slot == 11)
0423         return (pin == 1) ? AU1550_PCI_INTC : 0xff;
0424     if (slot == 12) {
0425         switch (pin) {
0426         case 1: return AU1550_PCI_INTB;
0427         case 2: return AU1550_PCI_INTC;
0428         case 3: return AU1550_PCI_INTD;
0429         case 4: return AU1550_PCI_INTA;
0430         }
0431     }
0432     if (slot == 13) {
0433         switch (pin) {
0434         case 1: return AU1550_PCI_INTA;
0435         case 2: return AU1550_PCI_INTB;
0436         case 3: return AU1550_PCI_INTC;
0437         case 4: return AU1550_PCI_INTD;
0438         }
0439     }
0440     return -1;
0441 }
0442 
0443 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
0444 {
0445     if ((slot < 12) || (slot > 13) || pin == 0)
0446         return -1;
0447     if (slot == 12) {
0448         switch (pin) {
0449         case 1: return AU1500_PCI_INTB;
0450         case 2: return AU1500_PCI_INTC;
0451         case 3: return AU1500_PCI_INTD;
0452         case 4: return AU1500_PCI_INTA;
0453         }
0454     }
0455     if (slot == 13) {
0456         switch (pin) {
0457         case 1: return AU1500_PCI_INTA;
0458         case 2: return AU1500_PCI_INTB;
0459         case 3: return AU1500_PCI_INTC;
0460         case 4: return AU1500_PCI_INTD;
0461         }
0462     }
0463     return -1;
0464 }
0465 
0466 static struct resource alchemy_pci_host_res[] = {
0467     [0] = {
0468         .start  = AU1500_PCI_PHYS_ADDR,
0469         .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
0470         .flags  = IORESOURCE_MEM,
0471     },
0472 };
0473 
0474 static struct alchemy_pci_platdata db1550_pci_pd = {
0475     .board_map_irq  = db1550_map_pci_irq,
0476 };
0477 
0478 static struct platform_device db1550_pci_host_dev = {
0479     .dev.platform_data = &db1550_pci_pd,
0480     .name       = "alchemy-pci",
0481     .id     = 0,
0482     .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
0483     .resource   = alchemy_pci_host_res,
0484 };
0485 
0486 /**********************************************************************/
0487 
0488 static struct platform_device *db1550_devs[] __initdata = {
0489     &db1550_i2c_dev,
0490     &db1550_ac97_dev,
0491     &db1550_spi_dev,
0492     &db1550_i2s_dev,
0493     &db1550_stac_dev,
0494     &db1550_ac97dma_dev,
0495     &db1550_i2sdma_dev,
0496     &db1550_sndac97_dev,
0497     &db1550_sndi2s_dev,
0498 };
0499 
0500 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
0501 int __init db1550_pci_setup(int id)
0502 {
0503     if (id)
0504         db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
0505     return platform_device_register(&db1550_pci_host_dev);
0506 }
0507 
0508 static void __init db1550_devices(void)
0509 {
0510     alchemy_gpio_direction_output(203, 0);  /* red led on */
0511 
0512     irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
0513     irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
0514     irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
0515     irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */
0516     irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
0517     irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
0518 
0519     db1x_register_pcmcia_socket(
0520         AU1000_PCMCIA_ATTR_PHYS_ADDR,
0521         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
0522         AU1000_PCMCIA_MEM_PHYS_ADDR,
0523         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
0524         AU1000_PCMCIA_IO_PHYS_ADDR,
0525         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
0526         AU1550_GPIO3_INT, 0,
0527         /*AU1550_GPIO21_INT*/0, 0, 0);
0528 
0529     db1x_register_pcmcia_socket(
0530         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
0531         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
0532         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
0533         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
0534         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
0535         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
0536         AU1550_GPIO5_INT, 1,
0537         /*AU1550_GPIO22_INT*/0, 0, 1);
0538 
0539     platform_device_register(&db1550_nand_dev);
0540 
0541     alchemy_gpio_direction_output(202, 0);  /* green led on */
0542 }
0543 
0544 static void __init pb1550_devices(void)
0545 {
0546     irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
0547     irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
0548     irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
0549 
0550     /* enable both PCMCIA card irqs in the shared line */
0551     alchemy_gpio2_enable_int(201);  /* socket 0 card irq */
0552     alchemy_gpio2_enable_int(202);  /* socket 1 card irq */
0553 
0554     /* Pb1550, like all others, also has statuschange irqs; however they're
0555     * wired up on one of the Au1550's shared GPIO201_205 line, which also
0556     * services the PCMCIA card interrupts.  So we ignore statuschange and
0557     * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
0558     * drivers are used to shared irqs and b) statuschange isn't really use-
0559     * ful anyway.
0560     */
0561     db1x_register_pcmcia_socket(
0562         AU1000_PCMCIA_ATTR_PHYS_ADDR,
0563         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
0564         AU1000_PCMCIA_MEM_PHYS_ADDR,
0565         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
0566         AU1000_PCMCIA_IO_PHYS_ADDR,
0567         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
0568         AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
0569 
0570     db1x_register_pcmcia_socket(
0571         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
0572         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
0573         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
0574         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
0575         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008000000,
0576         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
0577         AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
0578 
0579     pb1550_nand_setup();
0580 }
0581 
0582 int __init db1550_dev_setup(void)
0583 {
0584     int swapped, id;
0585     struct clk *c;
0586 
0587     id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
0588 
0589     i2c_register_board_info(0, db1550_i2c_devs,
0590                 ARRAY_SIZE(db1550_i2c_devs));
0591     spi_register_board_info(db1550_spi_devs,
0592                 ARRAY_SIZE(db1550_i2c_devs));
0593 
0594     c = clk_get(NULL, "psc0_intclk");
0595     if (!IS_ERR(c)) {
0596         clk_set_rate(c, 50000000);
0597         clk_prepare_enable(c);
0598         clk_put(c);
0599     }
0600     c = clk_get(NULL, "psc2_intclk");
0601     if (!IS_ERR(c)) {
0602         clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
0603         clk_prepare_enable(c);
0604         clk_put(c);
0605     }
0606 
0607     /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
0608     __raw_writel(PSC_SEL_CLK_SERCLK,
0609         (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
0610     wmb();
0611     __raw_writel(PSC_SEL_CLK_SERCLK,
0612         (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
0613     wmb();
0614     /* SPI/I2C use internally supplied 50MHz source */
0615     __raw_writel(PSC_SEL_CLK_INTCLK,
0616         (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
0617     wmb();
0618     __raw_writel(PSC_SEL_CLK_INTCLK,
0619         (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
0620     wmb();
0621 
0622     id ? pb1550_devices() : db1550_devices();
0623 
0624     swapped = bcsr_read(BCSR_STATUS) &
0625            (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
0626     db1x_register_norflash(128 << 20, 4, swapped);
0627 
0628     return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
0629 }
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