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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * DBAu1200/PBAu1200 board platform device registration
0004  *
0005  * Copyright (C) 2008-2011 Manuel Lauss
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/gpio.h>
0011 #include <linux/i2c.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/leds.h>
0017 #include <linux/mmc/host.h>
0018 #include <linux/mtd/mtd.h>
0019 #include <linux/mtd/platnand.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/serial_8250.h>
0022 #include <linux/spi/spi.h>
0023 #include <linux/spi/flash.h>
0024 #include <linux/smc91x.h>
0025 #include <linux/ata_platform.h>
0026 #include <asm/mach-au1x00/au1000.h>
0027 #include <asm/mach-au1x00/au1100_mmc.h>
0028 #include <asm/mach-au1x00/au1xxx_dbdma.h>
0029 #include <asm/mach-au1x00/au1xxx_psc.h>
0030 #include <asm/mach-au1x00/au1200fb.h>
0031 #include <asm/mach-au1x00/au1550_spi.h>
0032 #include <asm/mach-db1x00/bcsr.h>
0033 
0034 #include "platform.h"
0035 
0036 #define BCSR_INT_IDE        0x0001
0037 #define BCSR_INT_ETH        0x0002
0038 #define BCSR_INT_PC0        0x0004
0039 #define BCSR_INT_PC0STSCHG  0x0008
0040 #define BCSR_INT_PC1        0x0010
0041 #define BCSR_INT_PC1STSCHG  0x0020
0042 #define BCSR_INT_DC     0x0040
0043 #define BCSR_INT_FLASHBUSY  0x0080
0044 #define BCSR_INT_PC0INSERT  0x0100
0045 #define BCSR_INT_PC0EJECT   0x0200
0046 #define BCSR_INT_PC1INSERT  0x0400
0047 #define BCSR_INT_PC1EJECT   0x0800
0048 #define BCSR_INT_SD0INSERT  0x1000
0049 #define BCSR_INT_SD0EJECT   0x2000
0050 #define BCSR_INT_SD1INSERT  0x4000
0051 #define BCSR_INT_SD1EJECT   0x8000
0052 
0053 #define DB1200_IDE_PHYS_ADDR    0x18800000
0054 #define DB1200_IDE_REG_SHIFT    5
0055 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
0056 #define DB1200_ETH_PHYS_ADDR    0x19000300
0057 #define DB1200_NAND_PHYS_ADDR   0x20000000
0058 
0059 #define PB1200_IDE_PHYS_ADDR    0x0C800000
0060 #define PB1200_ETH_PHYS_ADDR    0x0D000300
0061 #define PB1200_NAND_PHYS_ADDR   0x1C000000
0062 
0063 #define DB1200_INT_BEGIN    (AU1000_MAX_INTR + 1)
0064 #define DB1200_IDE_INT      (DB1200_INT_BEGIN + 0)
0065 #define DB1200_ETH_INT      (DB1200_INT_BEGIN + 1)
0066 #define DB1200_PC0_INT      (DB1200_INT_BEGIN + 2)
0067 #define DB1200_PC0_STSCHG_INT   (DB1200_INT_BEGIN + 3)
0068 #define DB1200_PC1_INT      (DB1200_INT_BEGIN + 4)
0069 #define DB1200_PC1_STSCHG_INT   (DB1200_INT_BEGIN + 5)
0070 #define DB1200_DC_INT       (DB1200_INT_BEGIN + 6)
0071 #define DB1200_FLASHBUSY_INT    (DB1200_INT_BEGIN + 7)
0072 #define DB1200_PC0_INSERT_INT   (DB1200_INT_BEGIN + 8)
0073 #define DB1200_PC0_EJECT_INT    (DB1200_INT_BEGIN + 9)
0074 #define DB1200_PC1_INSERT_INT   (DB1200_INT_BEGIN + 10)
0075 #define DB1200_PC1_EJECT_INT    (DB1200_INT_BEGIN + 11)
0076 #define DB1200_SD0_INSERT_INT   (DB1200_INT_BEGIN + 12)
0077 #define DB1200_SD0_EJECT_INT    (DB1200_INT_BEGIN + 13)
0078 #define PB1200_SD1_INSERT_INT   (DB1200_INT_BEGIN + 14)
0079 #define PB1200_SD1_EJECT_INT    (DB1200_INT_BEGIN + 15)
0080 #define DB1200_INT_END      (DB1200_INT_BEGIN + 15)
0081 
0082 const char *get_system_type(void);
0083 
0084 static int __init db1200_detect_board(void)
0085 {
0086     int bid;
0087 
0088     /* try the DB1200 first */
0089     bcsr_init(DB1200_BCSR_PHYS_ADDR,
0090           DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
0091     if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
0092         unsigned short t = bcsr_read(BCSR_HEXLEDS);
0093         bcsr_write(BCSR_HEXLEDS, ~t);
0094         if (bcsr_read(BCSR_HEXLEDS) != t) {
0095             bcsr_write(BCSR_HEXLEDS, t);
0096             return 0;
0097         }
0098     }
0099 
0100     /* okay, try the PB1200 then */
0101     bcsr_init(PB1200_BCSR_PHYS_ADDR,
0102           PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
0103     bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
0104     if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
0105         (bid == BCSR_WHOAMI_PB1200_DDR2)) {
0106         unsigned short t = bcsr_read(BCSR_HEXLEDS);
0107         bcsr_write(BCSR_HEXLEDS, ~t);
0108         if (bcsr_read(BCSR_HEXLEDS) != t) {
0109             bcsr_write(BCSR_HEXLEDS, t);
0110             return 0;
0111         }
0112     }
0113 
0114     return 1;   /* it's neither */
0115 }
0116 
0117 int __init db1200_board_setup(void)
0118 {
0119     unsigned short whoami;
0120 
0121     if (db1200_detect_board())
0122         return -ENODEV;
0123 
0124     whoami = bcsr_read(BCSR_WHOAMI);
0125     switch (BCSR_WHOAMI_BOARD(whoami)) {
0126     case BCSR_WHOAMI_PB1200_DDR1:
0127     case BCSR_WHOAMI_PB1200_DDR2:
0128     case BCSR_WHOAMI_DB1200:
0129         break;
0130     default:
0131         return -ENODEV;
0132     }
0133 
0134     printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
0135         "  Board-ID %d  Daughtercard ID %d\n", get_system_type(),
0136         (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
0137 
0138     return 0;
0139 }
0140 
0141 /******************************************************************************/
0142 
0143 static u64 au1200_all_dmamask = DMA_BIT_MASK(32);
0144 
0145 static struct mtd_partition db1200_spiflash_parts[] = {
0146     {
0147         .name   = "spi_flash",
0148         .offset = 0,
0149         .size   = MTDPART_SIZ_FULL,
0150     },
0151 };
0152 
0153 static struct flash_platform_data db1200_spiflash_data = {
0154     .name       = "s25fl001",
0155     .parts      = db1200_spiflash_parts,
0156     .nr_parts   = ARRAY_SIZE(db1200_spiflash_parts),
0157     .type       = "m25p10",
0158 };
0159 
0160 static struct spi_board_info db1200_spi_devs[] __initdata = {
0161     {
0162         /* TI TMP121AIDBVR temp sensor */
0163         .modalias   = "tmp121",
0164         .max_speed_hz   = 2000000,
0165         .bus_num    = 0,
0166         .chip_select    = 0,
0167         .mode       = 0,
0168     },
0169     {
0170         /* Spansion S25FL001D0FMA SPI flash */
0171         .modalias   = "m25p80",
0172         .max_speed_hz   = 50000000,
0173         .bus_num    = 0,
0174         .chip_select    = 1,
0175         .mode       = 0,
0176         .platform_data  = &db1200_spiflash_data,
0177     },
0178 };
0179 
0180 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
0181     { I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */
0182     { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
0183     { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
0184 };
0185 
0186 /**********************************************************************/
0187 
0188 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd,
0189                  unsigned int ctrl)
0190 {
0191     unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
0192 
0193     ioaddr &= 0xffffff00;
0194 
0195     if (ctrl & NAND_CLE) {
0196         ioaddr += MEM_STNAND_CMD;
0197     } else if (ctrl & NAND_ALE) {
0198         ioaddr += MEM_STNAND_ADDR;
0199     } else {
0200         /* assume we want to r/w real data  by default */
0201         ioaddr += MEM_STNAND_DATA;
0202     }
0203     this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
0204     if (cmd != NAND_CMD_NONE) {
0205         __raw_writeb(cmd, this->legacy.IO_ADDR_W);
0206         wmb();
0207     }
0208 }
0209 
0210 static int au1200_nand_device_ready(struct nand_chip *this)
0211 {
0212     return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
0213 }
0214 
0215 static struct mtd_partition db1200_nand_parts[] = {
0216     {
0217         .name   = "NAND FS 0",
0218         .offset = 0,
0219         .size   = 8 * 1024 * 1024,
0220     },
0221     {
0222         .name   = "NAND FS 1",
0223         .offset = MTDPART_OFS_APPEND,
0224         .size   = MTDPART_SIZ_FULL
0225     },
0226 };
0227 
0228 struct platform_nand_data db1200_nand_platdata = {
0229     .chip = {
0230         .nr_chips   = 1,
0231         .chip_offset    = 0,
0232         .nr_partitions  = ARRAY_SIZE(db1200_nand_parts),
0233         .partitions = db1200_nand_parts,
0234         .chip_delay = 20,
0235     },
0236     .ctrl = {
0237         .dev_ready  = au1200_nand_device_ready,
0238         .cmd_ctrl   = au1200_nand_cmd_ctrl,
0239     },
0240 };
0241 
0242 static struct resource db1200_nand_res[] = {
0243     [0] = {
0244         .start  = DB1200_NAND_PHYS_ADDR,
0245         .end    = DB1200_NAND_PHYS_ADDR + 0xff,
0246         .flags  = IORESOURCE_MEM,
0247     },
0248 };
0249 
0250 static struct platform_device db1200_nand_dev = {
0251     .name       = "gen_nand",
0252     .num_resources  = ARRAY_SIZE(db1200_nand_res),
0253     .resource   = db1200_nand_res,
0254     .id     = -1,
0255     .dev        = {
0256         .platform_data = &db1200_nand_platdata,
0257     }
0258 };
0259 
0260 /**********************************************************************/
0261 
0262 static struct smc91x_platdata db1200_eth_data = {
0263     .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
0264     .leda   = RPC_LED_100_10,
0265     .ledb   = RPC_LED_TX_RX,
0266 };
0267 
0268 static struct resource db1200_eth_res[] = {
0269     [0] = {
0270         .start  = DB1200_ETH_PHYS_ADDR,
0271         .end    = DB1200_ETH_PHYS_ADDR + 0xf,
0272         .flags  = IORESOURCE_MEM,
0273     },
0274     [1] = {
0275         .start  = DB1200_ETH_INT,
0276         .end    = DB1200_ETH_INT,
0277         .flags  = IORESOURCE_IRQ,
0278     },
0279 };
0280 
0281 static struct platform_device db1200_eth_dev = {
0282     .dev    = {
0283         .platform_data  = &db1200_eth_data,
0284     },
0285     .name       = "smc91x",
0286     .id     = -1,
0287     .num_resources  = ARRAY_SIZE(db1200_eth_res),
0288     .resource   = db1200_eth_res,
0289 };
0290 
0291 /**********************************************************************/
0292 
0293 static struct pata_platform_info db1200_ide_info = {
0294     .ioport_shift   = DB1200_IDE_REG_SHIFT,
0295 };
0296 
0297 #define IDE_ALT_START   (14 << DB1200_IDE_REG_SHIFT)
0298 static struct resource db1200_ide_res[] = {
0299     [0] = {
0300         .start  = DB1200_IDE_PHYS_ADDR,
0301         .end    = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
0302         .flags  = IORESOURCE_MEM,
0303     },
0304     [1] = {
0305         .start  = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
0306         .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
0307         .flags  = IORESOURCE_MEM,
0308     },
0309     [2] = {
0310         .start  = DB1200_IDE_INT,
0311         .end    = DB1200_IDE_INT,
0312         .flags  = IORESOURCE_IRQ,
0313     },
0314 };
0315 
0316 static struct platform_device db1200_ide_dev = {
0317     .name       = "pata_platform",
0318     .id     = 0,
0319     .dev = {
0320         .dma_mask       = &au1200_all_dmamask,
0321         .coherent_dma_mask  = DMA_BIT_MASK(32),
0322         .platform_data      = &db1200_ide_info,
0323     },
0324     .num_resources  = ARRAY_SIZE(db1200_ide_res),
0325     .resource   = db1200_ide_res,
0326 };
0327 
0328 /**********************************************************************/
0329 
0330 /* SD carddetects:  they're supposed to be edge-triggered, but ack
0331  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
0332  * is disabled and its counterpart enabled.  The 200ms timeout is
0333  * because the carddetect usually triggers twice, after debounce.
0334  */
0335 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
0336 {
0337     disable_irq_nosync(irq);
0338     return IRQ_WAKE_THREAD;
0339 }
0340 
0341 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
0342 {
0343     void (*mmc_cd)(struct mmc_host *, unsigned long);
0344 
0345     /* link against CONFIG_MMC=m */
0346     mmc_cd = symbol_get(mmc_detect_change);
0347     if (mmc_cd) {
0348         mmc_cd(ptr, msecs_to_jiffies(200));
0349         symbol_put(mmc_detect_change);
0350     }
0351 
0352     msleep(100);    /* debounce */
0353     if (irq == DB1200_SD0_INSERT_INT)
0354         enable_irq(DB1200_SD0_EJECT_INT);
0355     else
0356         enable_irq(DB1200_SD0_INSERT_INT);
0357 
0358     return IRQ_HANDLED;
0359 }
0360 
0361 static int db1200_mmc_cd_setup(void *mmc_host, int en)
0362 {
0363     int ret;
0364 
0365     if (en) {
0366         ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
0367                 db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
0368         if (ret)
0369             goto out;
0370 
0371         ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
0372                 db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
0373         if (ret) {
0374             free_irq(DB1200_SD0_INSERT_INT, mmc_host);
0375             goto out;
0376         }
0377 
0378         if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
0379             enable_irq(DB1200_SD0_EJECT_INT);
0380         else
0381             enable_irq(DB1200_SD0_INSERT_INT);
0382 
0383     } else {
0384         free_irq(DB1200_SD0_INSERT_INT, mmc_host);
0385         free_irq(DB1200_SD0_EJECT_INT, mmc_host);
0386     }
0387     ret = 0;
0388 out:
0389     return ret;
0390 }
0391 
0392 static void db1200_mmc_set_power(void *mmc_host, int state)
0393 {
0394     if (state) {
0395         bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
0396         msleep(400);    /* stabilization time */
0397     } else
0398         bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
0399 }
0400 
0401 static int db1200_mmc_card_readonly(void *mmc_host)
0402 {
0403     return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
0404 }
0405 
0406 static int db1200_mmc_card_inserted(void *mmc_host)
0407 {
0408     return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
0409 }
0410 
0411 static void db1200_mmcled_set(struct led_classdev *led,
0412                   enum led_brightness brightness)
0413 {
0414     if (brightness != LED_OFF)
0415         bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
0416     else
0417         bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
0418 }
0419 
0420 static struct led_classdev db1200_mmc_led = {
0421     .brightness_set = db1200_mmcled_set,
0422 };
0423 
0424 /* -- */
0425 
0426 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
0427 {
0428     disable_irq_nosync(irq);
0429     return IRQ_WAKE_THREAD;
0430 }
0431 
0432 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
0433 {
0434     void (*mmc_cd)(struct mmc_host *, unsigned long);
0435 
0436     /* link against CONFIG_MMC=m */
0437     mmc_cd = symbol_get(mmc_detect_change);
0438     if (mmc_cd) {
0439         mmc_cd(ptr, msecs_to_jiffies(200));
0440         symbol_put(mmc_detect_change);
0441     }
0442 
0443     msleep(100);    /* debounce */
0444     if (irq == PB1200_SD1_INSERT_INT)
0445         enable_irq(PB1200_SD1_EJECT_INT);
0446     else
0447         enable_irq(PB1200_SD1_INSERT_INT);
0448 
0449     return IRQ_HANDLED;
0450 }
0451 
0452 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
0453 {
0454     int ret;
0455 
0456     if (en) {
0457         ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
0458                 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
0459         if (ret)
0460             goto out;
0461 
0462         ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
0463                 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
0464         if (ret) {
0465             free_irq(PB1200_SD1_INSERT_INT, mmc_host);
0466             goto out;
0467         }
0468 
0469         if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
0470             enable_irq(PB1200_SD1_EJECT_INT);
0471         else
0472             enable_irq(PB1200_SD1_INSERT_INT);
0473 
0474     } else {
0475         free_irq(PB1200_SD1_INSERT_INT, mmc_host);
0476         free_irq(PB1200_SD1_EJECT_INT, mmc_host);
0477     }
0478     ret = 0;
0479 out:
0480     return ret;
0481 }
0482 
0483 static void pb1200_mmc1led_set(struct led_classdev *led,
0484             enum led_brightness brightness)
0485 {
0486     if (brightness != LED_OFF)
0487             bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
0488     else
0489             bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
0490 }
0491 
0492 static struct led_classdev pb1200_mmc1_led = {
0493     .brightness_set = pb1200_mmc1led_set,
0494 };
0495 
0496 static void pb1200_mmc1_set_power(void *mmc_host, int state)
0497 {
0498     if (state) {
0499         bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
0500         msleep(400);    /* stabilization time */
0501     } else
0502         bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
0503 }
0504 
0505 static int pb1200_mmc1_card_readonly(void *mmc_host)
0506 {
0507     return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
0508 }
0509 
0510 static int pb1200_mmc1_card_inserted(void *mmc_host)
0511 {
0512     return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
0513 }
0514 
0515 
0516 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
0517     [0] = {
0518         .cd_setup   = db1200_mmc_cd_setup,
0519         .set_power  = db1200_mmc_set_power,
0520         .card_inserted  = db1200_mmc_card_inserted,
0521         .card_readonly  = db1200_mmc_card_readonly,
0522         .led        = &db1200_mmc_led,
0523     },
0524     [1] = {
0525         .cd_setup   = pb1200_mmc1_cd_setup,
0526         .set_power  = pb1200_mmc1_set_power,
0527         .card_inserted  = pb1200_mmc1_card_inserted,
0528         .card_readonly  = pb1200_mmc1_card_readonly,
0529         .led        = &pb1200_mmc1_led,
0530     },
0531 };
0532 
0533 static struct resource au1200_mmc0_resources[] = {
0534     [0] = {
0535         .start  = AU1100_SD0_PHYS_ADDR,
0536         .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
0537         .flags  = IORESOURCE_MEM,
0538     },
0539     [1] = {
0540         .start  = AU1200_SD_INT,
0541         .end    = AU1200_SD_INT,
0542         .flags  = IORESOURCE_IRQ,
0543     },
0544     [2] = {
0545         .start  = AU1200_DSCR_CMD0_SDMS_TX0,
0546         .end    = AU1200_DSCR_CMD0_SDMS_TX0,
0547         .flags  = IORESOURCE_DMA,
0548     },
0549     [3] = {
0550         .start  = AU1200_DSCR_CMD0_SDMS_RX0,
0551         .end    = AU1200_DSCR_CMD0_SDMS_RX0,
0552         .flags  = IORESOURCE_DMA,
0553     }
0554 };
0555 
0556 static struct platform_device db1200_mmc0_dev = {
0557     .name       = "au1xxx-mmc",
0558     .id     = 0,
0559     .dev = {
0560         .dma_mask       = &au1200_all_dmamask,
0561         .coherent_dma_mask  = DMA_BIT_MASK(32),
0562         .platform_data      = &db1200_mmc_platdata[0],
0563     },
0564     .num_resources  = ARRAY_SIZE(au1200_mmc0_resources),
0565     .resource   = au1200_mmc0_resources,
0566 };
0567 
0568 static struct resource au1200_mmc1_res[] = {
0569     [0] = {
0570         .start  = AU1100_SD1_PHYS_ADDR,
0571         .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
0572         .flags  = IORESOURCE_MEM,
0573     },
0574     [1] = {
0575         .start  = AU1200_SD_INT,
0576         .end    = AU1200_SD_INT,
0577         .flags  = IORESOURCE_IRQ,
0578     },
0579     [2] = {
0580         .start  = AU1200_DSCR_CMD0_SDMS_TX1,
0581         .end    = AU1200_DSCR_CMD0_SDMS_TX1,
0582         .flags  = IORESOURCE_DMA,
0583     },
0584     [3] = {
0585         .start  = AU1200_DSCR_CMD0_SDMS_RX1,
0586         .end    = AU1200_DSCR_CMD0_SDMS_RX1,
0587         .flags  = IORESOURCE_DMA,
0588     }
0589 };
0590 
0591 static struct platform_device pb1200_mmc1_dev = {
0592     .name       = "au1xxx-mmc",
0593     .id     = 1,
0594     .dev = {
0595         .dma_mask       = &au1200_all_dmamask,
0596         .coherent_dma_mask  = DMA_BIT_MASK(32),
0597         .platform_data      = &db1200_mmc_platdata[1],
0598     },
0599     .num_resources  = ARRAY_SIZE(au1200_mmc1_res),
0600     .resource   = au1200_mmc1_res,
0601 };
0602 
0603 /**********************************************************************/
0604 
0605 static int db1200fb_panel_index(void)
0606 {
0607     return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
0608 }
0609 
0610 static int db1200fb_panel_init(void)
0611 {
0612     /* Apply power */
0613     bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
0614                 BCSR_BOARD_LCDBL);
0615     return 0;
0616 }
0617 
0618 static int db1200fb_panel_shutdown(void)
0619 {
0620     /* Remove power */
0621     bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
0622                  BCSR_BOARD_LCDBL, 0);
0623     return 0;
0624 }
0625 
0626 static struct au1200fb_platdata db1200fb_pd = {
0627     .panel_index    = db1200fb_panel_index,
0628     .panel_init = db1200fb_panel_init,
0629     .panel_shutdown = db1200fb_panel_shutdown,
0630 };
0631 
0632 static struct resource au1200_lcd_res[] = {
0633     [0] = {
0634         .start  = AU1200_LCD_PHYS_ADDR,
0635         .end    = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
0636         .flags  = IORESOURCE_MEM,
0637     },
0638     [1] = {
0639         .start  = AU1200_LCD_INT,
0640         .end    = AU1200_LCD_INT,
0641         .flags  = IORESOURCE_IRQ,
0642     }
0643 };
0644 
0645 static struct platform_device au1200_lcd_dev = {
0646     .name       = "au1200-lcd",
0647     .id     = 0,
0648     .dev = {
0649         .dma_mask       = &au1200_all_dmamask,
0650         .coherent_dma_mask  = DMA_BIT_MASK(32),
0651         .platform_data      = &db1200fb_pd,
0652     },
0653     .num_resources  = ARRAY_SIZE(au1200_lcd_res),
0654     .resource   = au1200_lcd_res,
0655 };
0656 
0657 /**********************************************************************/
0658 
0659 static struct resource au1200_psc0_res[] = {
0660     [0] = {
0661         .start  = AU1550_PSC0_PHYS_ADDR,
0662         .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
0663         .flags  = IORESOURCE_MEM,
0664     },
0665     [1] = {
0666         .start  = AU1200_PSC0_INT,
0667         .end    = AU1200_PSC0_INT,
0668         .flags  = IORESOURCE_IRQ,
0669     },
0670     [2] = {
0671         .start  = AU1200_DSCR_CMD0_PSC0_TX,
0672         .end    = AU1200_DSCR_CMD0_PSC0_TX,
0673         .flags  = IORESOURCE_DMA,
0674     },
0675     [3] = {
0676         .start  = AU1200_DSCR_CMD0_PSC0_RX,
0677         .end    = AU1200_DSCR_CMD0_PSC0_RX,
0678         .flags  = IORESOURCE_DMA,
0679     },
0680 };
0681 
0682 static struct platform_device db1200_i2c_dev = {
0683     .name       = "au1xpsc_smbus",
0684     .id     = 0,    /* bus number */
0685     .num_resources  = ARRAY_SIZE(au1200_psc0_res),
0686     .resource   = au1200_psc0_res,
0687 };
0688 
0689 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
0690 {
0691     if (cs)
0692         bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
0693     else
0694         bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
0695 }
0696 
0697 static struct au1550_spi_info db1200_spi_platdata = {
0698     .mainclk_hz = 50000000, /* PSC0 clock */
0699     .num_chipselect = 2,
0700     .activate_cs    = db1200_spi_cs_en,
0701 };
0702 
0703 static struct platform_device db1200_spi_dev = {
0704     .dev    = {
0705         .dma_mask       = &au1200_all_dmamask,
0706         .coherent_dma_mask  = DMA_BIT_MASK(32),
0707         .platform_data      = &db1200_spi_platdata,
0708     },
0709     .name       = "au1550-spi",
0710     .id     = 0,    /* bus number */
0711     .num_resources  = ARRAY_SIZE(au1200_psc0_res),
0712     .resource   = au1200_psc0_res,
0713 };
0714 
0715 static struct resource au1200_psc1_res[] = {
0716     [0] = {
0717         .start  = AU1550_PSC1_PHYS_ADDR,
0718         .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
0719         .flags  = IORESOURCE_MEM,
0720     },
0721     [1] = {
0722         .start  = AU1200_PSC1_INT,
0723         .end    = AU1200_PSC1_INT,
0724         .flags  = IORESOURCE_IRQ,
0725     },
0726     [2] = {
0727         .start  = AU1200_DSCR_CMD0_PSC1_TX,
0728         .end    = AU1200_DSCR_CMD0_PSC1_TX,
0729         .flags  = IORESOURCE_DMA,
0730     },
0731     [3] = {
0732         .start  = AU1200_DSCR_CMD0_PSC1_RX,
0733         .end    = AU1200_DSCR_CMD0_PSC1_RX,
0734         .flags  = IORESOURCE_DMA,
0735     },
0736 };
0737 
0738 /* AC97 or I2S device */
0739 static struct platform_device db1200_audio_dev = {
0740     /* name assigned later based on switch setting */
0741     .id     = 1,    /* PSC ID */
0742     .num_resources  = ARRAY_SIZE(au1200_psc1_res),
0743     .resource   = au1200_psc1_res,
0744 };
0745 
0746 /* DB1200 ASoC card device */
0747 static struct platform_device db1200_sound_dev = {
0748     /* name assigned later based on switch setting */
0749     .id     = 1,    /* PSC ID */
0750     .dev = {
0751         .dma_mask       = &au1200_all_dmamask,
0752         .coherent_dma_mask  = DMA_BIT_MASK(32),
0753     },
0754 };
0755 
0756 static struct platform_device db1200_stac_dev = {
0757     .name       = "ac97-codec",
0758     .id     = 1,    /* on PSC1 */
0759 };
0760 
0761 static struct platform_device db1200_audiodma_dev = {
0762     .name       = "au1xpsc-pcm",
0763     .id     = 1,    /* PSC ID */
0764 };
0765 
0766 static struct platform_device *db1200_devs[] __initdata = {
0767     NULL,       /* PSC0, selected by S6.8 */
0768     &db1200_ide_dev,
0769     &db1200_mmc0_dev,
0770     &au1200_lcd_dev,
0771     &db1200_eth_dev,
0772     &db1200_nand_dev,
0773     &db1200_audiodma_dev,
0774     &db1200_audio_dev,
0775     &db1200_stac_dev,
0776     &db1200_sound_dev,
0777 };
0778 
0779 static struct platform_device *pb1200_devs[] __initdata = {
0780     &pb1200_mmc1_dev,
0781 };
0782 
0783 /* Some peripheral base addresses differ on the PB1200 */
0784 static int __init pb1200_res_fixup(void)
0785 {
0786     /* CPLD Revs earlier than 4 cause problems */
0787     if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
0788         printk(KERN_ERR "WARNING!!!\n");
0789         printk(KERN_ERR "WARNING!!!\n");
0790         printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
0791         printk(KERN_ERR "the board updated to latest revisions.\n");
0792         printk(KERN_ERR "This software will not work reliably\n");
0793         printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
0794         printk(KERN_ERR "WARNING!!!\n");
0795         printk(KERN_ERR "WARNING!!!\n");
0796         return 1;
0797     }
0798 
0799     db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
0800     db1200_nand_res[0].end   = PB1200_NAND_PHYS_ADDR + 0xff;
0801     db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
0802     db1200_ide_res[0].end   = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
0803     db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
0804     db1200_eth_res[0].end   = PB1200_ETH_PHYS_ADDR + 0xff;
0805     return 0;
0806 }
0807 
0808 int __init db1200_dev_setup(void)
0809 {
0810     unsigned long pfc;
0811     unsigned short sw;
0812     int swapped, bid;
0813     struct clk *c;
0814 
0815     bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
0816     if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
0817         (bid == BCSR_WHOAMI_PB1200_DDR2)) {
0818         if (pb1200_res_fixup())
0819             return -ENODEV;
0820     }
0821 
0822     /* GPIO7 is low-level triggered CPLD cascade */
0823     irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
0824     bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
0825 
0826     /* SMBus/SPI on PSC0, Audio on PSC1 */
0827     pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
0828     pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
0829     pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
0830     pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
0831     alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
0832 
0833     /* get 50MHz for I2C driver on PSC0 */
0834     c = clk_get(NULL, "psc0_intclk");
0835     if (!IS_ERR(c)) {
0836         pfc = clk_round_rate(c, 50000000);
0837         if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
0838             pr_warn("DB1200: can't get I2C close to 50MHz\n");
0839         else
0840             clk_set_rate(c, pfc);
0841         clk_prepare_enable(c);
0842         clk_put(c);
0843     }
0844 
0845     /* insert/eject pairs: one of both is always screaming.  To avoid
0846      * issues they must not be automatically enabled when initially
0847      * requested.
0848      */
0849     irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
0850     irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
0851     irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
0852     irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
0853     irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
0854     irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
0855 
0856     i2c_register_board_info(0, db1200_i2c_devs,
0857                 ARRAY_SIZE(db1200_i2c_devs));
0858     spi_register_board_info(db1200_spi_devs,
0859                 ARRAY_SIZE(db1200_i2c_devs));
0860 
0861     /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
0862      *      S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
0863      *      or S12 on the PB1200.
0864      */
0865 
0866     /* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
0867      * this pin is claimed by PSC0 (unused though, but pinmux doesn't
0868      * allow to free it without crippling the SPI interface).
0869      * As a result, in SPI mode, OTG simply won't work (PSC0 uses
0870      * it as an input pin which is pulled high on the boards).
0871      */
0872     pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
0873 
0874     /* switch off OTG VBUS supply */
0875     gpio_request(215, "otg-vbus");
0876     gpio_direction_output(215, 1);
0877 
0878     printk(KERN_INFO "%s device configuration:\n", get_system_type());
0879 
0880     sw = bcsr_read(BCSR_SWITCHES);
0881     if (sw & BCSR_SWITCHES_DIP_8) {
0882         db1200_devs[0] = &db1200_i2c_dev;
0883         bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
0884 
0885         pfc |= (2 << 17);   /* GPIO2 block owns GPIO215 */
0886 
0887         printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
0888         printk(KERN_INFO "   OTG port VBUS supply available!\n");
0889     } else {
0890         db1200_devs[0] = &db1200_spi_dev;
0891         bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
0892 
0893         pfc |= (1 << 17);   /* PSC0 owns GPIO215 */
0894 
0895         printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
0896         printk(KERN_INFO "   OTG port VBUS supply disabled\n");
0897     }
0898     alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
0899 
0900     /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
0901      * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
0902      */
0903     sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
0904     if (sw == BCSR_SWITCHES_DIP_8) {
0905         bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
0906         db1200_audio_dev.name = "au1xpsc_i2s";
0907         db1200_sound_dev.name = "db1200-i2s";
0908         printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
0909     } else {
0910         bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
0911         db1200_audio_dev.name = "au1xpsc_ac97";
0912         db1200_sound_dev.name = "db1200-ac97";
0913         printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
0914     }
0915 
0916     /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
0917     __raw_writel(PSC_SEL_CLK_SERCLK,
0918         (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
0919     wmb();
0920 
0921     db1x_register_pcmcia_socket(
0922         AU1000_PCMCIA_ATTR_PHYS_ADDR,
0923         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
0924         AU1000_PCMCIA_MEM_PHYS_ADDR,
0925         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
0926         AU1000_PCMCIA_IO_PHYS_ADDR,
0927         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
0928         DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
0929         /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
0930 
0931     db1x_register_pcmcia_socket(
0932         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
0933         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
0934         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
0935         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
0936         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
0937         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
0938         DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
0939         /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
0940 
0941     swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
0942     db1x_register_norflash(64 << 20, 2, swapped);
0943 
0944     platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
0945 
0946     /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
0947     if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
0948         (bid == BCSR_WHOAMI_PB1200_DDR2))
0949         platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
0950 
0951     return 0;
0952 }
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