alchemy/devboards/bcsr.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
0004  *
0005  * All Alchemy development boards (except, of course, the weird PB1000)
0006  * have a few registers in a CPLD with standardised layout; they mostly
0007  * only differ in base address.
0008  * All registers are 16bits wide with 32bit spacing.
0009  */
0010
0011 #include <linux/interrupt.h>
0012 #include <linux/irqchip/chained_irq.h>
0013 #include <linux/init.h>
0014 #include <linux/export.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/irq.h>
0017 #include <asm/addrspace.h>
0018 #include <asm/io.h>
0019 #include <asm/mach-db1x00/bcsr.h>
0020
0021 static struct bcsr_reg {
0022     void __iomem *raddr;
0023     spinlock_t lock;
0024 } bcsr_regs[BCSR_CNT];
0025
0026 static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
0027 static int bcsr_csc_base;   /* linux-irq of first cascaded irq */
0028
0029 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
0030 {
0031     int i;
0032
0033     bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
0034     bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
0035
0036     bcsr_virt = (void __iomem *)bcsr1_phys;
0037
0038     for (i = 0; i < BCSR_CNT; i++) {
0039         if (i >= BCSR_HEXLEDS)
0040             bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
0041                     (0x04 * (i - BCSR_HEXLEDS));
0042         else
0043             bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
0044                     (0x04 * i);
0045
0046         spin_lock_init(&bcsr_regs[i].lock);
0047     }
0048 }
0049
0050 unsigned short bcsr_read(enum bcsr_id reg)
0051 {
0052     unsigned short r;
0053     unsigned long flags;
0054
0055     spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
0056     r = __raw_readw(bcsr_regs[reg].raddr);
0057     spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
0058     return r;
0059 }
0060 EXPORT_SYMBOL_GPL(bcsr_read);
0061
0062 void bcsr_write(enum bcsr_id reg, unsigned short val)
0063 {
0064     unsigned long flags;
0065
0066     spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
0067     __raw_writew(val, bcsr_regs[reg].raddr);
0068     wmb();
0069     spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
0070 }
0071 EXPORT_SYMBOL_GPL(bcsr_write);
0072
0073 void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
0074 {
0075     unsigned short r;
0076     unsigned long flags;
0077
0078     spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
0079     r = __raw_readw(bcsr_regs[reg].raddr);
0080     r &= ~clr;
0081     r |= set;
0082     __raw_writew(r, bcsr_regs[reg].raddr);
0083     wmb();
0084     spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
0085 }
0086 EXPORT_SYMBOL_GPL(bcsr_mod);
0087
0088 /*
0089  * DB1200/PB1200 CPLD IRQ muxer
0090  */
0091 static void bcsr_csc_handler(struct irq_desc *d)
0092 {
0093     unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
0094     struct irq_chip *chip = irq_desc_get_chip(d);
0095
0096     chained_irq_enter(chip, d);
0097     generic_handle_irq(bcsr_csc_base + __ffs(bisr));
0098     chained_irq_exit(chip, d);
0099 }
0100
0101 static void bcsr_irq_mask(struct irq_data *d)
0102 {
0103     unsigned short v = 1 << (d->irq - bcsr_csc_base);
0104     __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
0105     wmb();
0106 }
0107
0108 static void bcsr_irq_maskack(struct irq_data *d)
0109 {
0110     unsigned short v = 1 << (d->irq - bcsr_csc_base);
0111     __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
0112     __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT);  /* ack */
0113     wmb();
0114 }
0115
0116 static void bcsr_irq_unmask(struct irq_data *d)
0117 {
0118     unsigned short v = 1 << (d->irq - bcsr_csc_base);
0119     __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
0120     wmb();
0121 }
0122
0123 static struct irq_chip bcsr_irq_type = {
0124     .name       = "CPLD",
0125     .irq_mask   = bcsr_irq_mask,
0126     .irq_mask_ack   = bcsr_irq_maskack,
0127     .irq_unmask = bcsr_irq_unmask,
0128 };
0129
0130 void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
0131 {
0132     unsigned int irq;
0133
0134     /* mask & enable & ack all */
0135     __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
0136     __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
0137     __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
0138     wmb();
0139
0140     bcsr_csc_base = csc_start;
0141
0142     for (irq = csc_start; irq <= csc_end; irq++)
0143         irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
0144                           handle_level_irq, "level");
0145
0146     irq_set_chained_handler(hook_irq, bcsr_csc_handler);
0147 }