alchemy/common/usb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * USB block power/access management abstraction.
0004  *
0005  * Au1000+: The OHCI block control register is at the far end of the OHCI memory
0006  *      area. Au1550 has OHCI on different base address. No need to handle
0007  *      UDC here.
0008  * Au1200:  one register to control access and clocks to O/EHCI, UDC and OTG
0009  *      as well as the PHY for EHCI and UDC.
0010  *
0011  */
0012
0013 #include <linux/clk.h>
0014 #include <linux/export.h>
0015 #include <linux/init.h>
0016 #include <linux/io.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/syscore_ops.h>
0019 #include <asm/cpu.h>
0020 #include <asm/mach-au1x00/au1000.h>
0021
0022 /* control register offsets */
0023 #define AU1000_OHCICFG  0x7fffc
0024 #define AU1550_OHCICFG  0x07ffc
0025 #define AU1200_USBCFG   0x04
0026
0027 /* Au1000 USB block config bits */
0028 #define USBHEN_RD   (1 << 4)        /* OHCI reset-done indicator */
0029 #define USBHEN_CE   (1 << 3)        /* OHCI block clock enable */
0030 #define USBHEN_E    (1 << 2)        /* OHCI block enable */
0031 #define USBHEN_C    (1 << 1)        /* OHCI block coherency bit */
0032 #define USBHEN_BE   (1 << 0)        /* OHCI Big-Endian */
0033
0034 /* Au1200 USB config bits */
0035 #define USBCFG_PFEN (1 << 31)       /* prefetch enable (undoc) */
0036 #define USBCFG_RDCOMB   (1 << 30)       /* read combining (undoc) */
0037 #define USBCFG_UNKNOWN  (5 << 20)       /* unknown, leave this way */
0038 #define USBCFG_SSD  (1 << 23)       /* serial short detect en */
0039 #define USBCFG_PPE  (1 << 19)       /* HS PHY PLL */
0040 #define USBCFG_UCE  (1 << 18)       /* UDC clock enable */
0041 #define USBCFG_ECE  (1 << 17)       /* EHCI clock enable */
0042 #define USBCFG_OCE  (1 << 16)       /* OHCI clock enable */
0043 #define USBCFG_FLA(x)   (((x) & 0x3f) << 8)
0044 #define USBCFG_UCAM (1 << 7)        /* coherent access (undoc) */
0045 #define USBCFG_GME  (1 << 6)        /* OTG mem access */
0046 #define USBCFG_DBE  (1 << 5)        /* UDC busmaster enable */
0047 #define USBCFG_DME  (1 << 4)        /* UDC mem enable */
0048 #define USBCFG_EBE  (1 << 3)        /* EHCI busmaster enable */
0049 #define USBCFG_EME  (1 << 2)        /* EHCI mem enable */
0050 #define USBCFG_OBE  (1 << 1)        /* OHCI busmaster enable */
0051 #define USBCFG_OME  (1 << 0)        /* OHCI mem enable */
0052 #define USBCFG_INIT_AU1200  (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
0053                  USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
0054                  USBCFG_GME | USBCFG_DBE | USBCFG_DME |        \
0055                  USBCFG_EBE | USBCFG_EME | USBCFG_OBE |        \
0056                  USBCFG_OME)
0057
0058 /* Au1300 USB config registers */
0059 #define USB_DWC_CTRL1       0x00
0060 #define USB_DWC_CTRL2       0x04
0061 #define USB_VBUS_TIMER      0x10
0062 #define USB_SBUS_CTRL       0x14
0063 #define USB_MSR_ERR     0x18
0064 #define USB_DWC_CTRL3       0x1C
0065 #define USB_DWC_CTRL4       0x20
0066 #define USB_OTG_STATUS      0x28
0067 #define USB_DWC_CTRL5       0x2C
0068 #define USB_DWC_CTRL6       0x30
0069 #define USB_DWC_CTRL7       0x34
0070 #define USB_PHY_STATUS      0xC0
0071 #define USB_INT_STATUS      0xC4
0072 #define USB_INT_ENABLE      0xC8
0073
0074 #define USB_DWC_CTRL1_OTGD  0x04 /* set to DISable OTG */
0075 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */
0076 #define USB_DWC_CTRL1_DCRS  0x01 /* set to ENable UDC */
0077
0078 #define USB_DWC_CTRL2_PHY1RS    0x04 /* set to enable PHY1 */
0079 #define USB_DWC_CTRL2_PHY0RS    0x02 /* set to enable PHY0 */
0080 #define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */
0081
0082 #define USB_DWC_CTRL3_OHCI1_CKEN    (1 << 19)
0083 #define USB_DWC_CTRL3_OHCI0_CKEN    (1 << 18)
0084 #define USB_DWC_CTRL3_EHCI0_CKEN    (1 << 17)
0085 #define USB_DWC_CTRL3_OTG0_CKEN     (1 << 16)
0086
0087 #define USB_SBUS_CTRL_SBCA      0x04 /* coherent access */
0088
0089 #define USB_INTEN_FORCE         0x20
0090 #define USB_INTEN_PHY           0x10
0091 #define USB_INTEN_UDC           0x08
0092 #define USB_INTEN_EHCI          0x04
0093 #define USB_INTEN_OHCI1         0x02
0094 #define USB_INTEN_OHCI0         0x01
0095
0096 static DEFINE_SPINLOCK(alchemy_usb_lock);
0097
0098 static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
0099 {
0100     unsigned long r, s;
0101
0102     r = __raw_readl(base + USB_DWC_CTRL2);
0103     s = __raw_readl(base + USB_DWC_CTRL3);
0104
0105     s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
0106         USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
0107
0108     if (enable) {
0109         /* simply enable all PHYs */
0110         r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
0111              USB_DWC_CTRL2_PHYRS;
0112         __raw_writel(r, base + USB_DWC_CTRL2);
0113         wmb();
0114     } else if (!s) {
0115         /* no USB block active, do disable all PHYs */
0116         r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
0117                USB_DWC_CTRL2_PHYRS);
0118         __raw_writel(r, base + USB_DWC_CTRL2);
0119         wmb();
0120     }
0121 }
0122
0123 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
0124 {
0125     unsigned long r;
0126
0127     if (enable) {
0128         __raw_writel(1, base + USB_DWC_CTRL7);  /* start OHCI clock */
0129         wmb();
0130
0131         r = __raw_readl(base + USB_DWC_CTRL3);  /* enable OHCI block */
0132         r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
0133                    : USB_DWC_CTRL3_OHCI1_CKEN;
0134         __raw_writel(r, base + USB_DWC_CTRL3);
0135         wmb();
0136
0137         __au1300_usb_phyctl(base, enable);  /* power up the PHYs */
0138
0139         r = __raw_readl(base + USB_INT_ENABLE);
0140         r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
0141         __raw_writel(r, base + USB_INT_ENABLE);
0142         wmb();
0143
0144         /* reset the OHCI start clock bit */
0145         __raw_writel(0, base + USB_DWC_CTRL7);
0146         wmb();
0147     } else {
0148         r = __raw_readl(base + USB_INT_ENABLE);
0149         r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
0150         __raw_writel(r, base + USB_INT_ENABLE);
0151         wmb();
0152
0153         r = __raw_readl(base + USB_DWC_CTRL3);
0154         r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
0155                  : USB_DWC_CTRL3_OHCI1_CKEN);
0156         __raw_writel(r, base + USB_DWC_CTRL3);
0157         wmb();
0158
0159         __au1300_usb_phyctl(base, enable);
0160     }
0161 }
0162
0163 static inline void __au1300_ehci_control(void __iomem *base, int enable)
0164 {
0165     unsigned long r;
0166
0167     if (enable) {
0168         r = __raw_readl(base + USB_DWC_CTRL3);
0169         r |= USB_DWC_CTRL3_EHCI0_CKEN;
0170         __raw_writel(r, base + USB_DWC_CTRL3);
0171         wmb();
0172
0173         r = __raw_readl(base + USB_DWC_CTRL1);
0174         r |= USB_DWC_CTRL1_HSTRS;
0175         __raw_writel(r, base + USB_DWC_CTRL1);
0176         wmb();
0177
0178         __au1300_usb_phyctl(base, enable);
0179
0180         r = __raw_readl(base + USB_INT_ENABLE);
0181         r |= USB_INTEN_EHCI;
0182         __raw_writel(r, base + USB_INT_ENABLE);
0183         wmb();
0184     } else {
0185         r = __raw_readl(base + USB_INT_ENABLE);
0186         r &= ~USB_INTEN_EHCI;
0187         __raw_writel(r, base + USB_INT_ENABLE);
0188         wmb();
0189
0190         r = __raw_readl(base + USB_DWC_CTRL1);
0191         r &= ~USB_DWC_CTRL1_HSTRS;
0192         __raw_writel(r, base + USB_DWC_CTRL1);
0193         wmb();
0194
0195         r = __raw_readl(base + USB_DWC_CTRL3);
0196         r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
0197         __raw_writel(r, base + USB_DWC_CTRL3);
0198         wmb();
0199
0200         __au1300_usb_phyctl(base, enable);
0201     }
0202 }
0203
0204 static inline void __au1300_udc_control(void __iomem *base, int enable)
0205 {
0206     unsigned long r;
0207
0208     if (enable) {
0209         r = __raw_readl(base + USB_DWC_CTRL1);
0210         r |= USB_DWC_CTRL1_DCRS;
0211         __raw_writel(r, base + USB_DWC_CTRL1);
0212         wmb();
0213
0214         __au1300_usb_phyctl(base, enable);
0215
0216         r = __raw_readl(base + USB_INT_ENABLE);
0217         r |= USB_INTEN_UDC;
0218         __raw_writel(r, base + USB_INT_ENABLE);
0219         wmb();
0220     } else {
0221         r = __raw_readl(base + USB_INT_ENABLE);
0222         r &= ~USB_INTEN_UDC;
0223         __raw_writel(r, base + USB_INT_ENABLE);
0224         wmb();
0225
0226         r = __raw_readl(base + USB_DWC_CTRL1);
0227         r &= ~USB_DWC_CTRL1_DCRS;
0228         __raw_writel(r, base + USB_DWC_CTRL1);
0229         wmb();
0230
0231         __au1300_usb_phyctl(base, enable);
0232     }
0233 }
0234
0235 static inline void __au1300_otg_control(void __iomem *base, int enable)
0236 {
0237     unsigned long r;
0238     if (enable) {
0239         r = __raw_readl(base + USB_DWC_CTRL3);
0240         r |= USB_DWC_CTRL3_OTG0_CKEN;
0241         __raw_writel(r, base + USB_DWC_CTRL3);
0242         wmb();
0243
0244         r = __raw_readl(base + USB_DWC_CTRL1);
0245         r &= ~USB_DWC_CTRL1_OTGD;
0246         __raw_writel(r, base + USB_DWC_CTRL1);
0247         wmb();
0248
0249         __au1300_usb_phyctl(base, enable);
0250     } else {
0251         r = __raw_readl(base + USB_DWC_CTRL1);
0252         r |= USB_DWC_CTRL1_OTGD;
0253         __raw_writel(r, base + USB_DWC_CTRL1);
0254         wmb();
0255
0256         r = __raw_readl(base + USB_DWC_CTRL3);
0257         r &= ~USB_DWC_CTRL3_OTG0_CKEN;
0258         __raw_writel(r, base + USB_DWC_CTRL3);
0259         wmb();
0260
0261         __au1300_usb_phyctl(base, enable);
0262     }
0263 }
0264
0265 static inline int au1300_usb_control(int block, int enable)
0266 {
0267     void __iomem *base =
0268         (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
0269     int ret = 0;
0270
0271     switch (block) {
0272     case ALCHEMY_USB_OHCI0:
0273         __au1300_ohci_control(base, enable, 0);
0274         break;
0275     case ALCHEMY_USB_OHCI1:
0276         __au1300_ohci_control(base, enable, 1);
0277         break;
0278     case ALCHEMY_USB_EHCI0:
0279         __au1300_ehci_control(base, enable);
0280         break;
0281     case ALCHEMY_USB_UDC0:
0282         __au1300_udc_control(base, enable);
0283         break;
0284     case ALCHEMY_USB_OTG0:
0285         __au1300_otg_control(base, enable);
0286         break;
0287     default:
0288         ret = -ENODEV;
0289     }
0290     return ret;
0291 }
0292
0293 static inline void au1300_usb_init(void)
0294 {
0295     void __iomem *base =
0296         (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
0297
0298     /* set some sane defaults.  Note: we don't fiddle with DWC_CTRL4
0299      * here at all: Port 2 routing (EHCI or UDC) must be set either
0300      * by boot firmware or platform init code; I can't autodetect
0301      * a sane setting.
0302      */
0303     __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
0304     wmb();
0305     __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
0306     wmb();
0307     __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
0308     wmb();
0309     __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
0310     wmb();
0311     /* set coherent access bit */
0312     __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
0313     wmb();
0314 }
0315
0316 static inline void __au1200_ohci_control(void __iomem *base, int enable)
0317 {
0318     unsigned long r = __raw_readl(base + AU1200_USBCFG);
0319     if (enable) {
0320         __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
0321         wmb();
0322         udelay(2000);
0323     } else {
0324         __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
0325         wmb();
0326         udelay(1000);
0327     }
0328 }
0329
0330 static inline void __au1200_ehci_control(void __iomem *base, int enable)
0331 {
0332     unsigned long r = __raw_readl(base + AU1200_USBCFG);
0333     if (enable) {
0334         __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
0335         wmb();
0336         udelay(1000);
0337     } else {
0338         if (!(r & USBCFG_UCE))      /* UDC also off? */
0339             r &= ~USBCFG_PPE;   /* yes: disable HS PHY PLL */
0340         __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
0341         wmb();
0342         udelay(1000);
0343     }
0344 }
0345
0346 static inline void __au1200_udc_control(void __iomem *base, int enable)
0347 {
0348     unsigned long r = __raw_readl(base + AU1200_USBCFG);
0349     if (enable) {
0350         __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
0351         wmb();
0352     } else {
0353         if (!(r & USBCFG_ECE))      /* EHCI also off? */
0354             r &= ~USBCFG_PPE;   /* yes: disable HS PHY PLL */
0355         __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
0356         wmb();
0357     }
0358 }
0359
0360 static inline int au1200_usb_control(int block, int enable)
0361 {
0362     void __iomem *base =
0363             (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
0364
0365     switch (block) {
0366     case ALCHEMY_USB_OHCI0:
0367         __au1200_ohci_control(base, enable);
0368         break;
0369     case ALCHEMY_USB_UDC0:
0370         __au1200_udc_control(base, enable);
0371         break;
0372     case ALCHEMY_USB_EHCI0:
0373         __au1200_ehci_control(base, enable);
0374         break;
0375     default:
0376         return -ENODEV;
0377     }
0378     return 0;
0379 }
0380
0381
0382 /* initialize USB block(s) to a known working state */
0383 static inline void au1200_usb_init(void)
0384 {
0385     void __iomem *base =
0386             (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
0387     __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
0388     wmb();
0389     udelay(1000);
0390 }
0391
0392 static inline int au1000_usb_init(unsigned long rb, int reg)
0393 {
0394     void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
0395     unsigned long r = __raw_readl(base);
0396     struct clk *c;
0397
0398     /* 48MHz check. Don't init if no one can provide it */
0399     c = clk_get(NULL, "usbh_clk");
0400     if (IS_ERR(c))
0401         return -ENODEV;
0402     if (clk_round_rate(c, 48000000) != 48000000) {
0403         clk_put(c);
0404         return -ENODEV;
0405     }
0406     if (clk_set_rate(c, 48000000)) {
0407         clk_put(c);
0408         return -ENODEV;
0409     }
0410     clk_put(c);
0411
0412 #if defined(__BIG_ENDIAN)
0413     r |= USBHEN_BE;
0414 #endif
0415     r |= USBHEN_C;
0416
0417     __raw_writel(r, base);
0418     wmb();
0419     udelay(1000);
0420
0421     return 0;
0422 }
0423
0424
0425 static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
0426 {
0427     void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
0428     unsigned long r = __raw_readl(base + creg);
0429     struct clk *c = clk_get(NULL, "usbh_clk");
0430
0431     if (IS_ERR(c))
0432         return;
0433
0434     if (enable) {
0435         if (clk_prepare_enable(c))
0436             goto out;
0437
0438         __raw_writel(r | USBHEN_CE, base + creg);
0439         wmb();
0440         udelay(1000);
0441         __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
0442         wmb();
0443         udelay(1000);
0444
0445         /* wait for reset complete (read reg twice: au1500 erratum) */
0446         while (__raw_readl(base + creg),
0447             !(__raw_readl(base + creg) & USBHEN_RD))
0448             udelay(1000);
0449     } else {
0450         __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
0451         wmb();
0452         clk_disable_unprepare(c);
0453     }
0454 out:
0455     clk_put(c);
0456 }
0457
0458 static inline int au1000_usb_control(int block, int enable, unsigned long rb,
0459                      int creg)
0460 {
0461     int ret = 0;
0462
0463     switch (block) {
0464     case ALCHEMY_USB_OHCI0:
0465         __au1xx0_ohci_control(enable, rb, creg);
0466         break;
0467     default:
0468         ret = -ENODEV;
0469     }
0470     return ret;
0471 }
0472
0473 /*
0474  * alchemy_usb_control - control Alchemy on-chip USB blocks
0475  * @block:  USB block to target
0476  * @enable: set 1 to enable a block, 0 to disable
0477  */
0478 int alchemy_usb_control(int block, int enable)
0479 {
0480     unsigned long flags;
0481     int ret;
0482
0483     spin_lock_irqsave(&alchemy_usb_lock, flags);
0484     switch (alchemy_get_cputype()) {
0485     case ALCHEMY_CPU_AU1000:
0486     case ALCHEMY_CPU_AU1500:
0487     case ALCHEMY_CPU_AU1100:
0488         ret = au1000_usb_control(block, enable,
0489             AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
0490         break;
0491     case ALCHEMY_CPU_AU1550:
0492         ret = au1000_usb_control(block, enable,
0493             AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
0494         break;
0495     case ALCHEMY_CPU_AU1200:
0496         ret = au1200_usb_control(block, enable);
0497         break;
0498     case ALCHEMY_CPU_AU1300:
0499         ret = au1300_usb_control(block, enable);
0500         break;
0501     default:
0502         ret = -ENODEV;
0503     }
0504     spin_unlock_irqrestore(&alchemy_usb_lock, flags);
0505     return ret;
0506 }
0507 EXPORT_SYMBOL_GPL(alchemy_usb_control);
0508
0509
0510 static unsigned long alchemy_usb_pmdata[2];
0511
0512 static void au1000_usb_pm(unsigned long br, int creg, int susp)
0513 {
0514     void __iomem *base = (void __iomem *)KSEG1ADDR(br);
0515
0516     if (susp) {
0517         alchemy_usb_pmdata[0] = __raw_readl(base + creg);
0518         /* There appears to be some undocumented reset register.... */
0519         __raw_writel(0, base + 0x04);
0520         wmb();
0521         __raw_writel(0, base + creg);
0522         wmb();
0523     } else {
0524         __raw_writel(alchemy_usb_pmdata[0], base + creg);
0525         wmb();
0526     }
0527 }
0528
0529 static void au1200_usb_pm(int susp)
0530 {
0531     void __iomem *base =
0532             (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
0533     if (susp) {
0534         /* save OTG_CAP/MUX registers which indicate port routing */
0535         /* FIXME: write an OTG driver to do that */
0536         alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
0537         alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
0538     } else {
0539         /* restore access to all MMIO areas */
0540         au1200_usb_init();
0541
0542         /* restore OTG_CAP/MUX registers */
0543         __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
0544         __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
0545         wmb();
0546     }
0547 }
0548
0549 static void au1300_usb_pm(int susp)
0550 {
0551     void __iomem *base =
0552             (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
0553     /* remember Port2 routing */
0554     if (susp) {
0555         alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
0556     } else {
0557         au1300_usb_init();
0558         __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
0559         wmb();
0560     }
0561 }
0562
0563 static void alchemy_usb_pm(int susp)
0564 {
0565     switch (alchemy_get_cputype()) {
0566     case ALCHEMY_CPU_AU1000:
0567     case ALCHEMY_CPU_AU1500:
0568     case ALCHEMY_CPU_AU1100:
0569         au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
0570         break;
0571     case ALCHEMY_CPU_AU1550:
0572         au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
0573         break;
0574     case ALCHEMY_CPU_AU1200:
0575         au1200_usb_pm(susp);
0576         break;
0577     case ALCHEMY_CPU_AU1300:
0578         au1300_usb_pm(susp);
0579         break;
0580     }
0581 }
0582
0583 static int alchemy_usb_suspend(void)
0584 {
0585     alchemy_usb_pm(1);
0586     return 0;
0587 }
0588
0589 static void alchemy_usb_resume(void)
0590 {
0591     alchemy_usb_pm(0);
0592 }
0593
0594 static struct syscore_ops alchemy_usb_pm_ops = {
0595     .suspend    = alchemy_usb_suspend,
0596     .resume     = alchemy_usb_resume,
0597 };
0598
0599 static int __init alchemy_usb_init(void)
0600 {
0601     int ret = 0;
0602
0603     switch (alchemy_get_cputype()) {
0604     case ALCHEMY_CPU_AU1000:
0605     case ALCHEMY_CPU_AU1500:
0606     case ALCHEMY_CPU_AU1100:
0607         ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,
0608                       AU1000_OHCICFG);
0609         break;
0610     case ALCHEMY_CPU_AU1550:
0611         ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,
0612                       AU1550_OHCICFG);
0613         break;
0614     case ALCHEMY_CPU_AU1200:
0615         au1200_usb_init();
0616         break;
0617     case ALCHEMY_CPU_AU1300:
0618         au1300_usb_init();
0619         break;
0620     }
0621
0622     if (!ret)
0623         register_syscore_ops(&alchemy_usb_pm_ops);
0624
0625     return ret;
0626 }
0627 arch_initcall(alchemy_usb_init);