alchemy/common/time.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
0004  *
0005  * Previous incarnations were:
0006  * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
0007  * Copied and modified Carsten Langgaard's time.c
0008  *
0009  * Carsten Langgaard, carstenl@mips.com
0010  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
0011  *
0012  * ########################################################################
0013  *
0014  * ########################################################################
0015  *
0016  * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
0017  * databooks).  Firmware/Board init code must enable the counters in the
0018  * counter control register, otherwise the CP0 counter clocksource/event
0019  * will be installed instead (and use of 'wait' instruction is prohibited).
0020  */
0021
0022 #include <linux/clockchips.h>
0023 #include <linux/clocksource.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/spinlock.h>
0026
0027 #include <asm/idle.h>
0028 #include <asm/processor.h>
0029 #include <asm/time.h>
0030 #include <asm/mach-au1x00/au1000.h>
0031
0032 /* 32kHz clock enabled and detected */
0033 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
0034
0035 static u64 au1x_counter1_read(struct clocksource *cs)
0036 {
0037     return alchemy_rdsys(AU1000_SYS_RTCREAD);
0038 }
0039
0040 static struct clocksource au1x_counter1_clocksource = {
0041     .name       = "alchemy-counter1",
0042     .read       = au1x_counter1_read,
0043     .mask       = CLOCKSOURCE_MASK(32),
0044     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0045     .rating     = 1500,
0046 };
0047
0048 static int au1x_rtcmatch2_set_next_event(unsigned long delta,
0049                      struct clock_event_device *cd)
0050 {
0051     delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
0052     /* wait for register access */
0053     while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
0054         ;
0055     alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
0056
0057     return 0;
0058 }
0059
0060 static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
0061 {
0062     struct clock_event_device *cd = dev_id;
0063     cd->event_handler(cd);
0064     return IRQ_HANDLED;
0065 }
0066
0067 static struct clock_event_device au1x_rtcmatch2_clockdev = {
0068     .name       = "rtcmatch2",
0069     .features   = CLOCK_EVT_FEAT_ONESHOT,
0070     .rating     = 1500,
0071     .set_next_event = au1x_rtcmatch2_set_next_event,
0072     .cpumask    = cpu_possible_mask,
0073 };
0074
0075 static int __init alchemy_time_init(unsigned int m2int)
0076 {
0077     struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
0078     unsigned long t;
0079
0080     au1x_rtcmatch2_clockdev.irq = m2int;
0081
0082     /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
0083      * has been detected.  If so install the rtcmatch2 clocksource,
0084      * otherwise don't bother.  Note that both bits being set is by
0085      * no means a definite guarantee that the counters actually work
0086      * (the 32S bit seems to be stuck set to 1 once a single clock-
0087      * edge is detected, hence the timeouts).
0088      */
0089     if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
0090         goto cntr_err;
0091
0092     /*
0093      * setup counter 1 (RTC) to tick at full speed
0094      */
0095     t = 0xffffff;
0096     while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
0097         asm volatile ("nop");
0098     if (!t)
0099         goto cntr_err;
0100
0101     alchemy_wrsys(0, AU1000_SYS_RTCTRIM);   /* 32.768 kHz */
0102
0103     t = 0xffffff;
0104     while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
0105         asm volatile ("nop");
0106     if (!t)
0107         goto cntr_err;
0108     alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
0109
0110     t = 0xffffff;
0111     while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
0112         asm volatile ("nop");
0113     if (!t)
0114         goto cntr_err;
0115
0116     /* register counter1 clocksource and event device */
0117     clocksource_register_hz(&au1x_counter1_clocksource, 32768);
0118
0119     cd->shift = 32;
0120     cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
0121     cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
0122     cd->max_delta_ticks = 0xffffffff;
0123     cd->min_delta_ns = clockevent_delta2ns(9, cd);
0124     cd->min_delta_ticks = 9;    /* ~0.28ms */
0125     clockevents_register_device(cd);
0126     if (request_irq(m2int, au1x_rtcmatch2_irq, IRQF_TIMER, "timer",
0127             &au1x_rtcmatch2_clockdev))
0128         pr_err("Failed to register timer interrupt\n");
0129
0130     printk(KERN_INFO "Alchemy clocksource installed\n");
0131
0132     return 0;
0133
0134 cntr_err:
0135     return -1;
0136 }
0137
0138 static int alchemy_m2inttab[] __initdata = {
0139     AU1000_RTC_MATCH2_INT,
0140     AU1500_RTC_MATCH2_INT,
0141     AU1100_RTC_MATCH2_INT,
0142     AU1550_RTC_MATCH2_INT,
0143     AU1200_RTC_MATCH2_INT,
0144     AU1300_RTC_MATCH2_INT,
0145 };
0146
0147 void __init plat_time_init(void)
0148 {
0149     int t;
0150
0151     t = alchemy_get_cputype();
0152     if (t == ALCHEMY_CPU_UNKNOWN ||
0153         alchemy_time_init(alchemy_m2inttab[t]))
0154         cpu_wait = NULL;    /* wait doesn't work with r4k timer */
0155 }