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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2001, 2007-2008 MontaVista Software Inc.
0003  * Author: MontaVista Software, Inc. <source@mvista.com>
0004  *
0005  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
0006  *
0007  *  This program is free software; you can redistribute  it and/or modify it
0008  *  under  the terms of  the GNU General  Public License as published by the
0009  *  Free Software Foundation;  either version 2 of the  License, or (at your
0010  *  option) any later version.
0011  *
0012  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0013  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0016  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  *  You should have received a copy of the  GNU General Public License along
0024  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0025  *  675 Mass Ave, Cambridge, MA 02139, USA.
0026  */
0027 
0028 #include <linux/export.h>
0029 #include <linux/init.h>
0030 #include <linux/interrupt.h>
0031 #include <linux/slab.h>
0032 #include <linux/syscore_ops.h>
0033 
0034 #include <asm/irq_cpu.h>
0035 #include <asm/mach-au1x00/au1000.h>
0036 #include <asm/mach-au1x00/gpio-au1300.h>
0037 
0038 /* Interrupt Controller register offsets */
0039 #define IC_CFG0RD   0x40
0040 #define IC_CFG0SET  0x40
0041 #define IC_CFG0CLR  0x44
0042 #define IC_CFG1RD   0x48
0043 #define IC_CFG1SET  0x48
0044 #define IC_CFG1CLR  0x4C
0045 #define IC_CFG2RD   0x50
0046 #define IC_CFG2SET  0x50
0047 #define IC_CFG2CLR  0x54
0048 #define IC_REQ0INT  0x54
0049 #define IC_SRCRD    0x58
0050 #define IC_SRCSET   0x58
0051 #define IC_SRCCLR   0x5C
0052 #define IC_REQ1INT  0x5C
0053 #define IC_ASSIGNRD 0x60
0054 #define IC_ASSIGNSET    0x60
0055 #define IC_ASSIGNCLR    0x64
0056 #define IC_WAKERD   0x68
0057 #define IC_WAKESET  0x68
0058 #define IC_WAKECLR  0x6C
0059 #define IC_MASKRD   0x70
0060 #define IC_MASKSET  0x70
0061 #define IC_MASKCLR  0x74
0062 #define IC_RISINGRD 0x78
0063 #define IC_RISINGCLR    0x78
0064 #define IC_FALLINGRD    0x7C
0065 #define IC_FALLINGCLR   0x7C
0066 #define IC_TESTBIT  0x80
0067 
0068 /* per-processor fixed function irqs */
0069 struct alchemy_irqmap {
0070     int irq;    /* linux IRQ number */
0071     int type;   /* IRQ_TYPE_ */
0072     int prio;   /* irq priority, 0 highest, 3 lowest */
0073     int internal;   /* GPIC: internal source (no ext. pin)? */
0074 };
0075 
0076 static int au1x_ic_settype(struct irq_data *d, unsigned int type);
0077 static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
0078 
0079 
0080 /* NOTE on interrupt priorities: The original writers of this code said:
0081  *
0082  * Because of the tight timing of SETUP token to reply transactions,
0083  * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
0084  * needs the highest priority.
0085  */
0086 struct alchemy_irqmap au1000_irqmap[] __initdata = {
0087     { AU1000_UART0_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0088     { AU1000_UART1_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0089     { AU1000_UART2_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0090     { AU1000_UART3_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0091     { AU1000_SSI0_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0092     { AU1000_SSI1_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0093     { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0094     { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0095     { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0096     { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0097     { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0098     { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0099     { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0100     { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0101     { AU1000_TOY_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0102     { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0103     { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0104     { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0105     { AU1000_RTC_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0106     { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0107     { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0108     { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
0109     { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0110     { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0111     { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
0112     { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
0113     { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0114     { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
0115     { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0116     { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0117     { AU1000_AC97C_INT,   IRQ_TYPE_EDGE_RISING, 1, 0 },
0118     { -1, },
0119 };
0120 
0121 struct alchemy_irqmap au1500_irqmap[] __initdata = {
0122     { AU1500_UART0_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0123     { AU1500_PCI_INTA,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0124     { AU1500_PCI_INTB,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0125     { AU1500_UART3_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0126     { AU1500_PCI_INTC,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0127     { AU1500_PCI_INTD,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0128     { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0129     { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0130     { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0131     { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0132     { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0133     { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0134     { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0135     { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0136     { AU1500_TOY_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0137     { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0138     { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0139     { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0140     { AU1500_RTC_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0141     { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0142     { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0143     { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
0144     { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
0145     { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
0146     { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0147     { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
0148     { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0149     { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0150     { AU1500_AC97C_INT,   IRQ_TYPE_EDGE_RISING, 1, 0 },
0151     { -1, },
0152 };
0153 
0154 struct alchemy_irqmap au1100_irqmap[] __initdata = {
0155     { AU1100_UART0_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0156     { AU1100_UART1_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0157     { AU1100_SD_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0158     { AU1100_UART3_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0159     { AU1100_SSI0_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0160     { AU1100_SSI1_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0161     { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0162     { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0163     { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0164     { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0165     { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0166     { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0167     { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0168     { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0169     { AU1100_TOY_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0170     { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0171     { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0172     { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0173     { AU1100_RTC_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0174     { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0175     { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0176     { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
0177     { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0178     { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0179     { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
0180     { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
0181     { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0182     { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
0183     { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0184     { AU1100_LCD_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0185     { AU1100_AC97C_INT,   IRQ_TYPE_EDGE_RISING, 1, 0 },
0186     { -1, },
0187 };
0188 
0189 struct alchemy_irqmap au1550_irqmap[] __initdata = {
0190     { AU1550_UART0_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0191     { AU1550_PCI_INTA,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0192     { AU1550_PCI_INTB,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0193     { AU1550_DDMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0194     { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0195     { AU1550_PCI_INTC,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0196     { AU1550_PCI_INTD,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0197     { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   1, 0 },
0198     { AU1550_UART1_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0199     { AU1550_UART3_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0200     { AU1550_PSC0_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0201     { AU1550_PSC1_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0202     { AU1550_PSC2_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0203     { AU1550_PSC3_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0204     { AU1550_TOY_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0205     { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0206     { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0207     { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0208     { AU1550_RTC_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0209     { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0210     { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0211     { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
0212     { AU1550_NAND_INT,    IRQ_TYPE_EDGE_RISING, 1, 0 },
0213     { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
0214     { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
0215     { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
0216     { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0217     { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0218     { -1, },
0219 };
0220 
0221 struct alchemy_irqmap au1200_irqmap[] __initdata = {
0222     { AU1200_UART0_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0223     { AU1200_SWT_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0224     { AU1200_SD_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0225     { AU1200_DDMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0226     { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0227     { AU1200_UART1_INT,   IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0228     { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0229     { AU1200_PSC0_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0230     { AU1200_PSC1_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0231     { AU1200_AES_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0232     { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0233     { AU1200_TOY_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0234     { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0235     { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0236     { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0237     { AU1200_RTC_INT,     IRQ_TYPE_EDGE_RISING, 1, 0 },
0238     { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0239     { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
0240     { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
0241     { AU1200_NAND_INT,    IRQ_TYPE_EDGE_RISING, 1, 0 },
0242     { AU1200_USB_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0243     { AU1200_LCD_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0244     { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
0245     { -1, },
0246 };
0247 
0248 static struct alchemy_irqmap au1300_irqmap[] __initdata = {
0249     /* multifunction: gpio pin or device */
0250     { AU1300_UART1_INT,  IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0251     { AU1300_UART2_INT,  IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0252     { AU1300_UART3_INT,  IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0253     { AU1300_SD1_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0254     { AU1300_SD2_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0255     { AU1300_PSC0_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0256     { AU1300_PSC1_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0257     { AU1300_PSC2_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0258     { AU1300_PSC3_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0259     { AU1300_NAND_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 0, },
0260     /* au1300 internal */
0261     { AU1300_DDMA_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0262     { AU1300_MMU_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0263     { AU1300_MPU_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0264     { AU1300_GPU_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0265     { AU1300_UDMA_INT,   IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0266     { AU1300_TOY_INT,    IRQ_TYPE_EDGE_RISING,  1, 1, },
0267     { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
0268     { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
0269     { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
0270     { AU1300_RTC_INT,    IRQ_TYPE_EDGE_RISING,  1, 1, },
0271     { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
0272     { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
0273     { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING,  0, 1, },
0274     { AU1300_UART0_INT,  IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0275     { AU1300_SD0_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0276     { AU1300_USB_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0277     { AU1300_LCD_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0278     { AU1300_BSA_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0279     { AU1300_MPE_INT,    IRQ_TYPE_EDGE_RISING,  1, 1, },
0280     { AU1300_ITE_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0281     { AU1300_AES_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0282     { AU1300_CIM_INT,    IRQ_TYPE_LEVEL_HIGH,   1, 1, },
0283     { -1, },    /* terminator */
0284 };
0285 
0286 /******************************************************************************/
0287 
0288 static void au1x_ic0_unmask(struct irq_data *d)
0289 {
0290     unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
0291     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
0292 
0293     __raw_writel(1 << bit, base + IC_MASKSET);
0294     __raw_writel(1 << bit, base + IC_WAKESET);
0295     wmb();
0296 }
0297 
0298 static void au1x_ic1_unmask(struct irq_data *d)
0299 {
0300     unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
0301     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
0302 
0303     __raw_writel(1 << bit, base + IC_MASKSET);
0304     __raw_writel(1 << bit, base + IC_WAKESET);
0305     wmb();
0306 }
0307 
0308 static void au1x_ic0_mask(struct irq_data *d)
0309 {
0310     unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
0311     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
0312 
0313     __raw_writel(1 << bit, base + IC_MASKCLR);
0314     __raw_writel(1 << bit, base + IC_WAKECLR);
0315     wmb();
0316 }
0317 
0318 static void au1x_ic1_mask(struct irq_data *d)
0319 {
0320     unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
0321     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
0322 
0323     __raw_writel(1 << bit, base + IC_MASKCLR);
0324     __raw_writel(1 << bit, base + IC_WAKECLR);
0325     wmb();
0326 }
0327 
0328 static void au1x_ic0_ack(struct irq_data *d)
0329 {
0330     unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
0331     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
0332 
0333     /*
0334      * This may assume that we don't get interrupts from
0335      * both edges at once, or if we do, that we don't care.
0336      */
0337     __raw_writel(1 << bit, base + IC_FALLINGCLR);
0338     __raw_writel(1 << bit, base + IC_RISINGCLR);
0339     wmb();
0340 }
0341 
0342 static void au1x_ic1_ack(struct irq_data *d)
0343 {
0344     unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
0345     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
0346 
0347     /*
0348      * This may assume that we don't get interrupts from
0349      * both edges at once, or if we do, that we don't care.
0350      */
0351     __raw_writel(1 << bit, base + IC_FALLINGCLR);
0352     __raw_writel(1 << bit, base + IC_RISINGCLR);
0353     wmb();
0354 }
0355 
0356 static void au1x_ic0_maskack(struct irq_data *d)
0357 {
0358     unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
0359     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
0360 
0361     __raw_writel(1 << bit, base + IC_WAKECLR);
0362     __raw_writel(1 << bit, base + IC_MASKCLR);
0363     __raw_writel(1 << bit, base + IC_RISINGCLR);
0364     __raw_writel(1 << bit, base + IC_FALLINGCLR);
0365     wmb();
0366 }
0367 
0368 static void au1x_ic1_maskack(struct irq_data *d)
0369 {
0370     unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
0371     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
0372 
0373     __raw_writel(1 << bit, base + IC_WAKECLR);
0374     __raw_writel(1 << bit, base + IC_MASKCLR);
0375     __raw_writel(1 << bit, base + IC_RISINGCLR);
0376     __raw_writel(1 << bit, base + IC_FALLINGCLR);
0377     wmb();
0378 }
0379 
0380 static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
0381 {
0382     int bit = d->irq - AU1000_INTC1_INT_BASE;
0383     unsigned long wakemsk, flags;
0384 
0385     /* only GPIO 0-7 can act as wakeup source.  Fortunately these
0386      * are wired up identically on all supported variants.
0387      */
0388     if ((bit < 0) || (bit > 7))
0389         return -EINVAL;
0390 
0391     local_irq_save(flags);
0392     wakemsk = alchemy_rdsys(AU1000_SYS_WAKEMSK);
0393     if (on)
0394         wakemsk |= 1 << bit;
0395     else
0396         wakemsk &= ~(1 << bit);
0397     alchemy_wrsys(wakemsk, AU1000_SYS_WAKEMSK);
0398     local_irq_restore(flags);
0399 
0400     return 0;
0401 }
0402 
0403 /*
0404  * irq_chips for both ICs; this way the mask handlers can be
0405  * as short as possible.
0406  */
0407 static struct irq_chip au1x_ic0_chip = {
0408     .name       = "Alchemy-IC0",
0409     .irq_ack    = au1x_ic0_ack,
0410     .irq_mask   = au1x_ic0_mask,
0411     .irq_mask_ack   = au1x_ic0_maskack,
0412     .irq_unmask = au1x_ic0_unmask,
0413     .irq_set_type   = au1x_ic_settype,
0414 };
0415 
0416 static struct irq_chip au1x_ic1_chip = {
0417     .name       = "Alchemy-IC1",
0418     .irq_ack    = au1x_ic1_ack,
0419     .irq_mask   = au1x_ic1_mask,
0420     .irq_mask_ack   = au1x_ic1_maskack,
0421     .irq_unmask = au1x_ic1_unmask,
0422     .irq_set_type   = au1x_ic_settype,
0423     .irq_set_wake   = au1x_ic1_setwake,
0424 };
0425 
0426 static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
0427 {
0428     struct irq_chip *chip;
0429     unsigned int bit, irq = d->irq;
0430     irq_flow_handler_t handler = NULL;
0431     unsigned char *name = NULL;
0432     void __iomem *base;
0433     int ret;
0434 
0435     if (irq >= AU1000_INTC1_INT_BASE) {
0436         bit = irq - AU1000_INTC1_INT_BASE;
0437         chip = &au1x_ic1_chip;
0438         base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
0439     } else {
0440         bit = irq - AU1000_INTC0_INT_BASE;
0441         chip = &au1x_ic0_chip;
0442         base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
0443     }
0444 
0445     if (bit > 31)
0446         return -EINVAL;
0447 
0448     ret = 0;
0449 
0450     switch (flow_type) {    /* cfgregs 2:1:0 */
0451     case IRQ_TYPE_EDGE_RISING:  /* 0:0:1 */
0452         __raw_writel(1 << bit, base + IC_CFG2CLR);
0453         __raw_writel(1 << bit, base + IC_CFG1CLR);
0454         __raw_writel(1 << bit, base + IC_CFG0SET);
0455         handler = handle_edge_irq;
0456         name = "riseedge";
0457         break;
0458     case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
0459         __raw_writel(1 << bit, base + IC_CFG2CLR);
0460         __raw_writel(1 << bit, base + IC_CFG1SET);
0461         __raw_writel(1 << bit, base + IC_CFG0CLR);
0462         handler = handle_edge_irq;
0463         name = "falledge";
0464         break;
0465     case IRQ_TYPE_EDGE_BOTH:    /* 0:1:1 */
0466         __raw_writel(1 << bit, base + IC_CFG2CLR);
0467         __raw_writel(1 << bit, base + IC_CFG1SET);
0468         __raw_writel(1 << bit, base + IC_CFG0SET);
0469         handler = handle_edge_irq;
0470         name = "bothedge";
0471         break;
0472     case IRQ_TYPE_LEVEL_HIGH:   /* 1:0:1 */
0473         __raw_writel(1 << bit, base + IC_CFG2SET);
0474         __raw_writel(1 << bit, base + IC_CFG1CLR);
0475         __raw_writel(1 << bit, base + IC_CFG0SET);
0476         handler = handle_level_irq;
0477         name = "hilevel";
0478         break;
0479     case IRQ_TYPE_LEVEL_LOW:    /* 1:1:0 */
0480         __raw_writel(1 << bit, base + IC_CFG2SET);
0481         __raw_writel(1 << bit, base + IC_CFG1SET);
0482         __raw_writel(1 << bit, base + IC_CFG0CLR);
0483         handler = handle_level_irq;
0484         name = "lowlevel";
0485         break;
0486     case IRQ_TYPE_NONE:     /* 0:0:0 */
0487         __raw_writel(1 << bit, base + IC_CFG2CLR);
0488         __raw_writel(1 << bit, base + IC_CFG1CLR);
0489         __raw_writel(1 << bit, base + IC_CFG0CLR);
0490         break;
0491     default:
0492         ret = -EINVAL;
0493     }
0494     irq_set_chip_handler_name_locked(d, chip, handler, name);
0495 
0496     wmb();
0497 
0498     return ret;
0499 }
0500 
0501 /******************************************************************************/
0502 
0503 /*
0504  * au1300_gpic_chgcfg - change PIN configuration.
0505  * @gpio:   pin to change (0-based GPIO number from datasheet).
0506  * @clr:    clear all bits set in 'clr'.
0507  * @set:    set these bits.
0508  *
0509  * modifies a pins' configuration register, bits set in @clr will
0510  * be cleared in the register, bits in @set will be set.
0511  */
0512 static inline void au1300_gpic_chgcfg(unsigned int gpio,
0513                       unsigned long clr,
0514                       unsigned long set)
0515 {
0516     void __iomem *r = AU1300_GPIC_ADDR;
0517     unsigned long l;
0518 
0519     r += gpio * 4;  /* offset into pin config array */
0520     l = __raw_readl(r + AU1300_GPIC_PINCFG);
0521     l &= ~clr;
0522     l |= set;
0523     __raw_writel(l, r + AU1300_GPIC_PINCFG);
0524     wmb();
0525 }
0526 
0527 /*
0528  * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl).
0529  * @pin:    pin (0-based GPIO number from datasheet).
0530  *
0531  * Assigns a GPIO pin to the GPIO controller, so its level can either
0532  * be read or set through the generic GPIO functions.
0533  * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1).
0534  * REVISIT: is this function really necessary?
0535  */
0536 void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio)
0537 {
0538     au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE);
0539 }
0540 EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio);
0541 
0542 /*
0543  * au1300_pinfunc_to_dev - assign a pin to the device function.
0544  * @pin:    pin (0-based GPIO number from datasheet).
0545  *
0546  * Assigns a GPIO pin to its associated device function; the pin will be
0547  * driven by the device and not through GPIO functions.
0548  */
0549 void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio)
0550 {
0551     void __iomem *r = AU1300_GPIC_ADDR;
0552     unsigned long bit;
0553 
0554     r += GPIC_GPIO_BANKOFF(gpio);
0555     bit = GPIC_GPIO_TO_BIT(gpio);
0556     __raw_writel(bit, r + AU1300_GPIC_DEVSEL);
0557     wmb();
0558 }
0559 EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev);
0560 
0561 /*
0562  * au1300_set_irq_priority -  set internal priority of IRQ.
0563  * @irq:    irq to set priority (linux irq number).
0564  * @p:      priority (0 = highest, 3 = lowest).
0565  */
0566 void au1300_set_irq_priority(unsigned int irq, int p)
0567 {
0568     irq -= ALCHEMY_GPIC_INT_BASE;
0569     au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p));
0570 }
0571 EXPORT_SYMBOL_GPL(au1300_set_irq_priority);
0572 
0573 /*
0574  * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers.
0575  * @dchan:  dbdma trigger select (0, 1).
0576  * @gpio:   pin to assign as trigger.
0577  *
0578  * DBDMA controller has 2 external trigger sources; this function
0579  * assigns a GPIO to the selected trigger.
0580  */
0581 void au1300_set_dbdma_gpio(int dchan, unsigned int gpio)
0582 {
0583     unsigned long r;
0584 
0585     if ((dchan >= 0) && (dchan <= 1)) {
0586         r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
0587         r &= ~(0xff << (8 * dchan));
0588         r |= (gpio & 0x7f) << (8 * dchan);
0589         __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
0590         wmb();
0591     }
0592 }
0593 
0594 static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow)
0595 {
0596     au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE,
0597                allow ? GPIC_CFG_IDLEWAKE : 0);
0598 }
0599 
0600 static void au1300_gpic_mask(struct irq_data *d)
0601 {
0602     void __iomem *r = AU1300_GPIC_ADDR;
0603     unsigned long bit, irq = d->irq;
0604 
0605     irq -= ALCHEMY_GPIC_INT_BASE;
0606     r += GPIC_GPIO_BANKOFF(irq);
0607     bit = GPIC_GPIO_TO_BIT(irq);
0608     __raw_writel(bit, r + AU1300_GPIC_IDIS);
0609     wmb();
0610 
0611     gpic_pin_set_idlewake(irq, 0);
0612 }
0613 
0614 static void au1300_gpic_unmask(struct irq_data *d)
0615 {
0616     void __iomem *r = AU1300_GPIC_ADDR;
0617     unsigned long bit, irq = d->irq;
0618 
0619     irq -= ALCHEMY_GPIC_INT_BASE;
0620 
0621     gpic_pin_set_idlewake(irq, 1);
0622 
0623     r += GPIC_GPIO_BANKOFF(irq);
0624     bit = GPIC_GPIO_TO_BIT(irq);
0625     __raw_writel(bit, r + AU1300_GPIC_IEN);
0626     wmb();
0627 }
0628 
0629 static void au1300_gpic_maskack(struct irq_data *d)
0630 {
0631     void __iomem *r = AU1300_GPIC_ADDR;
0632     unsigned long bit, irq = d->irq;
0633 
0634     irq -= ALCHEMY_GPIC_INT_BASE;
0635     r += GPIC_GPIO_BANKOFF(irq);
0636     bit = GPIC_GPIO_TO_BIT(irq);
0637     __raw_writel(bit, r + AU1300_GPIC_IPEND);   /* ack */
0638     __raw_writel(bit, r + AU1300_GPIC_IDIS);    /* mask */
0639     wmb();
0640 
0641     gpic_pin_set_idlewake(irq, 0);
0642 }
0643 
0644 static void au1300_gpic_ack(struct irq_data *d)
0645 {
0646     void __iomem *r = AU1300_GPIC_ADDR;
0647     unsigned long bit, irq = d->irq;
0648 
0649     irq -= ALCHEMY_GPIC_INT_BASE;
0650     r += GPIC_GPIO_BANKOFF(irq);
0651     bit = GPIC_GPIO_TO_BIT(irq);
0652     __raw_writel(bit, r + AU1300_GPIC_IPEND);   /* ack */
0653     wmb();
0654 }
0655 
0656 static struct irq_chip au1300_gpic = {
0657     .name       = "GPIOINT",
0658     .irq_ack    = au1300_gpic_ack,
0659     .irq_mask   = au1300_gpic_mask,
0660     .irq_mask_ack   = au1300_gpic_maskack,
0661     .irq_unmask = au1300_gpic_unmask,
0662     .irq_set_type   = au1300_gpic_settype,
0663 };
0664 
0665 static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
0666 {
0667     unsigned long s;
0668     unsigned char *name = NULL;
0669     irq_flow_handler_t hdl = NULL;
0670 
0671     switch (type) {
0672     case IRQ_TYPE_LEVEL_HIGH:
0673         s = GPIC_CFG_IC_LEVEL_HIGH;
0674         name = "high";
0675         hdl = handle_level_irq;
0676         break;
0677     case IRQ_TYPE_LEVEL_LOW:
0678         s = GPIC_CFG_IC_LEVEL_LOW;
0679         name = "low";
0680         hdl = handle_level_irq;
0681         break;
0682     case IRQ_TYPE_EDGE_RISING:
0683         s = GPIC_CFG_IC_EDGE_RISE;
0684         name = "posedge";
0685         hdl = handle_edge_irq;
0686         break;
0687     case IRQ_TYPE_EDGE_FALLING:
0688         s = GPIC_CFG_IC_EDGE_FALL;
0689         name = "negedge";
0690         hdl = handle_edge_irq;
0691         break;
0692     case IRQ_TYPE_EDGE_BOTH:
0693         s = GPIC_CFG_IC_EDGE_BOTH;
0694         name = "bothedge";
0695         hdl = handle_edge_irq;
0696         break;
0697     case IRQ_TYPE_NONE:
0698         s = GPIC_CFG_IC_OFF;
0699         name = "disabled";
0700         hdl = handle_level_irq;
0701         break;
0702     default:
0703         return -EINVAL;
0704     }
0705 
0706     irq_set_chip_handler_name_locked(d, &au1300_gpic, hdl, name);
0707 
0708     au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);
0709 
0710     return 0;
0711 }
0712 
0713 /******************************************************************************/
0714 
0715 static inline void ic_init(void __iomem *base)
0716 {
0717     /* initialize interrupt controller to a safe state */
0718     __raw_writel(0xffffffff, base + IC_CFG0CLR);
0719     __raw_writel(0xffffffff, base + IC_CFG1CLR);
0720     __raw_writel(0xffffffff, base + IC_CFG2CLR);
0721     __raw_writel(0xffffffff, base + IC_MASKCLR);
0722     __raw_writel(0xffffffff, base + IC_ASSIGNCLR);
0723     __raw_writel(0xffffffff, base + IC_WAKECLR);
0724     __raw_writel(0xffffffff, base + IC_SRCSET);
0725     __raw_writel(0xffffffff, base + IC_FALLINGCLR);
0726     __raw_writel(0xffffffff, base + IC_RISINGCLR);
0727     __raw_writel(0x00000000, base + IC_TESTBIT);
0728     wmb();
0729 }
0730 
0731 static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
0732 
0733 static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
0734 {
0735     d[0] = __raw_readl(base + IC_CFG0RD);
0736     d[1] = __raw_readl(base + IC_CFG1RD);
0737     d[2] = __raw_readl(base + IC_CFG2RD);
0738     d[3] = __raw_readl(base + IC_SRCRD);
0739     d[4] = __raw_readl(base + IC_ASSIGNRD);
0740     d[5] = __raw_readl(base + IC_WAKERD);
0741     d[6] = __raw_readl(base + IC_MASKRD);
0742     ic_init(base);      /* shut it up too while at it */
0743 }
0744 
0745 static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
0746 {
0747     ic_init(base);
0748 
0749     __raw_writel(d[0], base + IC_CFG0SET);
0750     __raw_writel(d[1], base + IC_CFG1SET);
0751     __raw_writel(d[2], base + IC_CFG2SET);
0752     __raw_writel(d[3], base + IC_SRCSET);
0753     __raw_writel(d[4], base + IC_ASSIGNSET);
0754     __raw_writel(d[5], base + IC_WAKESET);
0755     wmb();
0756 
0757     __raw_writel(d[6], base + IC_MASKSET);
0758     wmb();
0759 }
0760 
0761 static int alchemy_ic_suspend(void)
0762 {
0763     alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
0764                    alchemy_gpic_pmdata);
0765     alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
0766                    &alchemy_gpic_pmdata[7]);
0767     return 0;
0768 }
0769 
0770 static void alchemy_ic_resume(void)
0771 {
0772     alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
0773                   &alchemy_gpic_pmdata[7]);
0774     alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
0775                   alchemy_gpic_pmdata);
0776 }
0777 
0778 static int alchemy_gpic_suspend(void)
0779 {
0780     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
0781     int i;
0782 
0783     /* save 4 interrupt mask status registers */
0784     alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
0785     alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
0786     alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
0787     alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
0788 
0789     /* save misc register(s) */
0790     alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
0791 
0792     /* molto silenzioso */
0793     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
0794     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
0795     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
0796     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
0797     wmb();
0798 
0799     /* save pin/int-type configuration */
0800     base += AU1300_GPIC_PINCFG;
0801     for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
0802         alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
0803 
0804     wmb();
0805 
0806     return 0;
0807 }
0808 
0809 static void alchemy_gpic_resume(void)
0810 {
0811     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
0812     int i;
0813 
0814     /* disable all first */
0815     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
0816     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
0817     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
0818     __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
0819     wmb();
0820 
0821     /* restore pin/int-type configurations */
0822     base += AU1300_GPIC_PINCFG;
0823     for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
0824         __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
0825     wmb();
0826 
0827     /* restore misc register(s) */
0828     base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
0829     __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
0830     wmb();
0831 
0832     /* finally restore masks */
0833     __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
0834     __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
0835     __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
0836     __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
0837     wmb();
0838 }
0839 
0840 static struct syscore_ops alchemy_ic_pmops = {
0841     .suspend    = alchemy_ic_suspend,
0842     .resume     = alchemy_ic_resume,
0843 };
0844 
0845 static struct syscore_ops alchemy_gpic_pmops = {
0846     .suspend    = alchemy_gpic_suspend,
0847     .resume     = alchemy_gpic_resume,
0848 };
0849 
0850 /******************************************************************************/
0851 
0852 /* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
0853 #define DISP(name, base, addr)                            \
0854 static void au1000_##name##_dispatch(struct irq_desc *d)              \
0855 {                                         \
0856     unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr));       \
0857     if (likely(r))                                \
0858         generic_handle_irq(base + __ffs(r));                  \
0859     else                                      \
0860         spurious_interrupt();                         \
0861 }
0862 
0863 DISP(ic0r0, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ0INT)
0864 DISP(ic0r1, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ1INT)
0865 DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT)
0866 DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT)
0867 
0868 static void alchemy_gpic_dispatch(struct irq_desc *d)
0869 {
0870     int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
0871     generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i);
0872 }
0873 
0874 /******************************************************************************/
0875 
0876 static void __init au1000_init_irq(struct alchemy_irqmap *map)
0877 {
0878     unsigned int bit, irq_nr;
0879     void __iomem *base;
0880 
0881     ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
0882     ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
0883     register_syscore_ops(&alchemy_ic_pmops);
0884     mips_cpu_irq_init();
0885 
0886     /* register all 64 possible IC0+IC1 irq sources as type "none".
0887      * Use set_irq_type() to set edge/level behaviour at runtime.
0888      */
0889     for (irq_nr = AU1000_INTC0_INT_BASE;
0890          (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++)
0891         au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE);
0892 
0893     for (irq_nr = AU1000_INTC1_INT_BASE;
0894          (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++)
0895         au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE);
0896 
0897     /*
0898      * Initialize IC0, which is fixed per processor.
0899      */
0900     while (map->irq != -1) {
0901         irq_nr = map->irq;
0902 
0903         if (irq_nr >= AU1000_INTC1_INT_BASE) {
0904             bit = irq_nr - AU1000_INTC1_INT_BASE;
0905             base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR);
0906         } else {
0907             bit = irq_nr - AU1000_INTC0_INT_BASE;
0908             base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
0909         }
0910         if (map->prio == 0)
0911             __raw_writel(1 << bit, base + IC_ASSIGNSET);
0912 
0913         au1x_ic_settype(irq_get_irq_data(irq_nr), map->type);
0914         ++map;
0915     }
0916 
0917     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch);
0918     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch);
0919     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch);
0920     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch);
0921 }
0922 
0923 static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints)
0924 {
0925     int i;
0926     void __iomem *bank_base;
0927 
0928     register_syscore_ops(&alchemy_gpic_pmops);
0929     mips_cpu_irq_init();
0930 
0931     /* disable & ack all possible interrupt sources */
0932     for (i = 0; i < 4; i++) {
0933         bank_base = AU1300_GPIC_ADDR + (i * 4);
0934         __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
0935         wmb();
0936         __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
0937         wmb();
0938     }
0939 
0940     /* register an irq_chip for them, with 2nd highest priority */
0941     for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {
0942         au1300_set_irq_priority(i, 1);
0943         au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
0944     }
0945 
0946     /* setup known on-chip sources */
0947     while ((i = dints->irq) != -1) {
0948         au1300_gpic_settype(irq_get_irq_data(i), dints->type);
0949         au1300_set_irq_priority(i, dints->prio);
0950 
0951         if (dints->internal)
0952             au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);
0953 
0954         dints++;
0955     }
0956 
0957     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch);
0958     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch);
0959     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch);
0960     irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch);
0961 }
0962 
0963 /******************************************************************************/
0964 
0965 void __init arch_init_irq(void)
0966 {
0967     switch (alchemy_get_cputype()) {
0968     case ALCHEMY_CPU_AU1000:
0969         au1000_init_irq(au1000_irqmap);
0970         break;
0971     case ALCHEMY_CPU_AU1500:
0972         au1000_init_irq(au1500_irqmap);
0973         break;
0974     case ALCHEMY_CPU_AU1100:
0975         au1000_init_irq(au1100_irqmap);
0976         break;
0977     case ALCHEMY_CPU_AU1550:
0978         au1000_init_irq(au1550_irqmap);
0979         break;
0980     case ALCHEMY_CPU_AU1200:
0981         au1000_init_irq(au1200_irqmap);
0982         break;
0983     case ALCHEMY_CPU_AU1300:
0984         alchemy_gpic_init_irq(au1300_irqmap);
0985         break;
0986     default:
0987         pr_err("unknown Alchemy IRQ core\n");
0988         break;
0989     }
0990 }
0991 
0992 asmlinkage void plat_irq_dispatch(void)
0993 {
0994     unsigned long r = (read_c0_status() & read_c0_cause()) >> 8;
0995     do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff));
0996 }
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