alchemy/common/gpiolib.c

0001 /*
0002  *  Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
0003  *  GPIOLIB support for Alchemy chips.
0004  *
0005  *  This program is free software; you can redistribute  it and/or modify it
0006  *  under  the terms of  the GNU General  Public License as published by the
0007  *  Free Software Foundation;  either version 2 of the  License, or (at your
0008  *  option) any later version.
0009  *
0010  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0011  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0012  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0013  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0014  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0015  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0016  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0017  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0018  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0019  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0020  *
0021  *  You should have received a copy of the  GNU General Public License along
0022  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0023  *  675 Mass Ave, Cambridge, MA 02139, USA.
0024  *
0025  *  Notes :
0026  *  au1000 SoC have only one GPIO block : GPIO1
0027  *  Au1100, Au15x0, Au12x0 have a second one : GPIO2
0028  *  Au1300 is totally different: 1 block with up to 128 GPIOs
0029  */
0030
0031 #include <linux/init.h>
0032 #include <linux/kernel.h>
0033 #include <linux/types.h>
0034 #include <linux/gpio.h>
0035 #include <asm/mach-au1x00/gpio-au1000.h>
0036 #include <asm/mach-au1x00/gpio-au1300.h>
0037
0038 static int gpio2_get(struct gpio_chip *chip, unsigned offset)
0039 {
0040     return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
0041 }
0042
0043 static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
0044 {
0045     alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
0046 }
0047
0048 static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
0049 {
0050     return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
0051 }
0052
0053 static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
0054                   int value)
0055 {
0056     return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
0057                         value);
0058 }
0059
0060 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
0061 {
0062     return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
0063 }
0064
0065
0066 static int gpio1_get(struct gpio_chip *chip, unsigned offset)
0067 {
0068     return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
0069 }
0070
0071 static void gpio1_set(struct gpio_chip *chip,
0072                 unsigned offset, int value)
0073 {
0074     alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
0075 }
0076
0077 static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
0078 {
0079     return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
0080 }
0081
0082 static int gpio1_direction_output(struct gpio_chip *chip,
0083                     unsigned offset, int value)
0084 {
0085     return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
0086                          value);
0087 }
0088
0089 static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
0090 {
0091     return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
0092 }
0093
0094 struct gpio_chip alchemy_gpio_chip[] = {
0095     [0] = {
0096         .label          = "alchemy-gpio1",
0097         .direction_input    = gpio1_direction_input,
0098         .direction_output   = gpio1_direction_output,
0099         .get            = gpio1_get,
0100         .set            = gpio1_set,
0101         .to_irq         = gpio1_to_irq,
0102         .base           = ALCHEMY_GPIO1_BASE,
0103         .ngpio          = ALCHEMY_GPIO1_NUM,
0104     },
0105     [1] = {
0106         .label          = "alchemy-gpio2",
0107         .direction_input    = gpio2_direction_input,
0108         .direction_output   = gpio2_direction_output,
0109         .get            = gpio2_get,
0110         .set            = gpio2_set,
0111         .to_irq         = gpio2_to_irq,
0112         .base           = ALCHEMY_GPIO2_BASE,
0113         .ngpio          = ALCHEMY_GPIO2_NUM,
0114     },
0115 };
0116
0117 static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
0118 {
0119     return !!au1300_gpio_get_value(off + AU1300_GPIO_BASE);
0120 }
0121
0122 static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
0123 {
0124     au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
0125 }
0126
0127 static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
0128 {
0129     return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
0130 }
0131
0132 static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
0133                    int v)
0134 {
0135     return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
0136 }
0137
0138 static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
0139 {
0140     return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
0141 }
0142
0143 static struct gpio_chip au1300_gpiochip = {
0144     .label          = "alchemy-gpic",
0145     .direction_input    = alchemy_gpic_dir_input,
0146     .direction_output   = alchemy_gpic_dir_output,
0147     .get            = alchemy_gpic_get,
0148     .set            = alchemy_gpic_set,
0149     .to_irq         = alchemy_gpic_gpio_to_irq,
0150     .base           = AU1300_GPIO_BASE,
0151     .ngpio          = AU1300_GPIO_NUM,
0152 };
0153
0154 static int __init alchemy_gpiochip_init(void)
0155 {
0156     int ret = 0;
0157
0158     switch (alchemy_get_cputype()) {
0159     case ALCHEMY_CPU_AU1000:
0160         ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL);
0161         break;
0162     case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200:
0163         ret = gpiochip_add_data(&alchemy_gpio_chip[0], NULL);
0164         ret |= gpiochip_add_data(&alchemy_gpio_chip[1], NULL);
0165         break;
0166     case ALCHEMY_CPU_AU1300:
0167         ret = gpiochip_add_data(&au1300_gpiochip, NULL);
0168         break;
0169     }
0170     return ret;
0171 }
0172 arch_initcall(alchemy_gpiochip_init);