alchemy/common/dma.c

0001 /*
0002  *
0003  * BRIEF MODULE DESCRIPTION
0004  *      A DMA channel allocator for Au1x00. API is modeled loosely off of
0005  *      linux/kernel/dma.c.
0006  *
0007  * Copyright 2000, 2008 MontaVista Software Inc.
0008  * Author: MontaVista Software, Inc. <source@mvista.com>
0009  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
0010  *
0011  *  This program is free software; you can redistribute  it and/or modify it
0012  *  under  the terms of  the GNU General  Public License as published by the
0013  *  Free Software Foundation;  either version 2 of the  License, or (at your
0014  *  option) any later version.
0015  *
0016  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0017  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0018  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0019  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0020  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0021  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0022  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0023  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0024  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0025  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0026  *
0027  *  You should have received a copy of the  GNU General Public License along
0028  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0029  *  675 Mass Ave, Cambridge, MA 02139, USA.
0030  *
0031  */
0032
0033 #include <linux/init.h>
0034 #include <linux/export.h>
0035 #include <linux/kernel.h>
0036 #include <linux/errno.h>
0037 #include <linux/spinlock.h>
0038 #include <linux/interrupt.h>
0039
0040 #include <asm/mach-au1x00/au1000.h>
0041 #include <asm/mach-au1x00/au1000_dma.h>
0042
0043 /*
0044  * A note on resource allocation:
0045  *
0046  * All drivers needing DMA channels, should allocate and release them
0047  * through the public routines `request_dma()' and `free_dma()'.
0048  *
0049  * In order to avoid problems, all processes should allocate resources in
0050  * the same sequence and release them in the reverse order.
0051  *
0052  * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
0053  * When releasing them, first release the IRQ, then release the DMA. The
0054  * main reason for this order is that, if you are requesting the DMA buffer
0055  * done interrupt, you won't know the irq number until the DMA channel is
0056  * returned from request_dma.
0057  */
0058
0059 /* DMA Channel register block spacing */
0060 #define DMA_CHANNEL_LEN     0x00000100
0061
0062 DEFINE_SPINLOCK(au1000_dma_spin_lock);
0063
0064 struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
0065       {.dev_id = -1,},
0066       {.dev_id = -1,},
0067       {.dev_id = -1,},
0068       {.dev_id = -1,},
0069       {.dev_id = -1,},
0070       {.dev_id = -1,},
0071       {.dev_id = -1,},
0072       {.dev_id = -1,}
0073 };
0074 EXPORT_SYMBOL(au1000_dma_table);
0075
0076 /* Device FIFO addresses and default DMA modes */
0077 static const struct dma_dev {
0078     unsigned int fifo_addr;
0079     unsigned int dma_mode;
0080 } dma_dev_table[DMA_NUM_DEV] = {
0081     { AU1000_UART0_PHYS_ADDR + 0x04, DMA_DW8 },     /* UART0_TX */
0082     { AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR },    /* UART0_RX */
0083     { 0, 0 },   /* DMA_REQ0 */
0084     { 0, 0 },   /* DMA_REQ1 */
0085     { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 },     /* AC97 TX c */
0086     { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR },    /* AC97 RX c */
0087     { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC },    /* UART3_TX */
0088     { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
0089     { AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
0090     { AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
0091     { AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
0092     { AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
0093     { AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
0094     { AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
0095     /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
0096     { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC},  /* I2S TX */
0097     { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
0098 };
0099
0100 int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
0101              int length, int *eof, void *data)
0102 {
0103     int i, len = 0;
0104     struct dma_chan *chan;
0105
0106     for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
0107         chan = get_dma_chan(i);
0108         if (chan != NULL)
0109             len += sprintf(buf + len, "%2d: %s\n",
0110                        i, chan->dev_str);
0111     }
0112
0113     if (fpos >= len) {
0114         *start = buf;
0115         *eof = 1;
0116         return 0;
0117     }
0118     *start = buf + fpos;
0119     len -= fpos;
0120     if (len > length)
0121         return length;
0122     *eof = 1;
0123     return len;
0124 }
0125
0126 /* Device FIFO addresses and default DMA modes - 2nd bank */
0127 static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
0128     { AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 },      /* coherent */
0129     { AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */
0130     { AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 },      /* coherent */
0131     { AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }  /* coherent */
0132 };
0133
0134 void dump_au1000_dma_channel(unsigned int dmanr)
0135 {
0136     struct dma_chan *chan;
0137
0138     if (dmanr >= NUM_AU1000_DMA_CHANNELS)
0139         return;
0140     chan = &au1000_dma_table[dmanr];
0141
0142     printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
0143     printk(KERN_INFO "  mode = 0x%08x\n",
0144            __raw_readl(chan->io + DMA_MODE_SET));
0145     printk(KERN_INFO "  addr = 0x%08x\n",
0146            __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
0147     printk(KERN_INFO "  start0 = 0x%08x\n",
0148            __raw_readl(chan->io + DMA_BUFFER0_START));
0149     printk(KERN_INFO "  start1 = 0x%08x\n",
0150            __raw_readl(chan->io + DMA_BUFFER1_START));
0151     printk(KERN_INFO "  count0 = 0x%08x\n",
0152            __raw_readl(chan->io + DMA_BUFFER0_COUNT));
0153     printk(KERN_INFO "  count1 = 0x%08x\n",
0154            __raw_readl(chan->io + DMA_BUFFER1_COUNT));
0155 }
0156
0157 /*
0158  * Finds a free channel, and binds the requested device to it.
0159  * Returns the allocated channel number, or negative on error.
0160  * Requests the DMA done IRQ if irqhandler != NULL.
0161  */
0162 int request_au1000_dma(int dev_id, const char *dev_str,
0163                irq_handler_t irqhandler,
0164                unsigned long irqflags,
0165                void *irq_dev_id)
0166 {
0167     struct dma_chan *chan;
0168     const struct dma_dev *dev;
0169     int i, ret;
0170
0171     if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
0172         if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
0173             return -EINVAL;
0174     } else {
0175         if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
0176             return -EINVAL;
0177     }
0178
0179     for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
0180         if (au1000_dma_table[i].dev_id < 0)
0181             break;
0182
0183     if (i == NUM_AU1000_DMA_CHANNELS)
0184         return -ENODEV;
0185
0186     chan = &au1000_dma_table[i];
0187
0188     if (dev_id >= DMA_NUM_DEV) {
0189         dev_id -= DMA_NUM_DEV;
0190         dev = &dma_dev_table_bank2[dev_id];
0191     } else
0192         dev = &dma_dev_table[dev_id];
0193
0194     if (irqhandler) {
0195         chan->irq_dev = irq_dev_id;
0196         ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
0197                   chan->irq_dev);
0198         if (ret) {
0199             chan->irq_dev = NULL;
0200             return ret;
0201         }
0202     } else {
0203         chan->irq_dev = NULL;
0204     }
0205
0206     /* fill it in */
0207     chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
0208             i * DMA_CHANNEL_LEN);
0209     chan->dev_id = dev_id;
0210     chan->dev_str = dev_str;
0211     chan->fifo_addr = dev->fifo_addr;
0212     chan->mode = dev->dma_mode;
0213
0214     /* initialize the channel before returning */
0215     init_dma(i);
0216
0217     return i;
0218 }
0219 EXPORT_SYMBOL(request_au1000_dma);
0220
0221 void free_au1000_dma(unsigned int dmanr)
0222 {
0223     struct dma_chan *chan = get_dma_chan(dmanr);
0224
0225     if (!chan) {
0226         printk(KERN_ERR "Error trying to free DMA%d\n", dmanr);
0227         return;
0228     }
0229
0230     disable_dma(dmanr);
0231     if (chan->irq_dev)
0232         free_irq(chan->irq, chan->irq_dev);
0233
0234     chan->irq_dev = NULL;
0235     chan->dev_id = -1;
0236 }
0237 EXPORT_SYMBOL(free_au1000_dma);
0238
0239 static int __init au1000_dma_init(void)
0240 {
0241     int base, i;
0242
0243     switch (alchemy_get_cputype()) {
0244     case ALCHEMY_CPU_AU1000:
0245         base = AU1000_DMA_INT_BASE;
0246         break;
0247     case ALCHEMY_CPU_AU1500:
0248         base = AU1500_DMA_INT_BASE;
0249         break;
0250     case ALCHEMY_CPU_AU1100:
0251         base = AU1100_DMA_INT_BASE;
0252         break;
0253     default:
0254         goto out;
0255     }
0256
0257     for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
0258         au1000_dma_table[i].irq = base + i;
0259
0260     printk(KERN_INFO "Alchemy DMA initialized\n");
0261
0262 out:
0263     return 0;
0264 }
0265 arch_initcall(au1000_dma_init);