include/asm/barrier.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __ASM_CSKY_BARRIER_H
0004 #define __ASM_CSKY_BARRIER_H
0005
0006 #ifndef __ASSEMBLY__
0007
0008 #define nop()   asm volatile ("nop\n":::"memory")
0009
0010 #ifdef CONFIG_SMP
0011
0012 /*
0013  * bar.brwarws: ordering barrier for all load/store instructions
0014  *              before/after
0015  *
0016  * |31|30 26|25 21|20 16|15  10|9   5|4           0|
0017  *  1  10000 00000 00000 100001 00001 0 bw br aw ar
0018  *
0019  * b: before
0020  * a: after
0021  * r: read
0022  * w: write
0023  *
0024  * Here are all combinations:
0025  *
0026  * bar.brw
0027  * bar.br
0028  * bar.bw
0029  * bar.arw
0030  * bar.ar
0031  * bar.aw
0032  * bar.brwarw
0033  * bar.brarw
0034  * bar.bwarw
0035  * bar.brwar
0036  * bar.brwaw
0037  * bar.brar
0038  * bar.bwaw
0039  */
0040 #define FULL_FENCE      ".long 0x842fc000\n"
0041 #define ACQUIRE_FENCE       ".long 0x8427c000\n"
0042 #define RELEASE_FENCE       ".long 0x842ec000\n"
0043
0044 #define __bar_brw() asm volatile (".long 0x842cc000\n":::"memory")
0045 #define __bar_br()  asm volatile (".long 0x8424c000\n":::"memory")
0046 #define __bar_bw()  asm volatile (".long 0x8428c000\n":::"memory")
0047 #define __bar_arw() asm volatile (".long 0x8423c000\n":::"memory")
0048 #define __bar_ar()  asm volatile (".long 0x8421c000\n":::"memory")
0049 #define __bar_aw()  asm volatile (".long 0x8422c000\n":::"memory")
0050 #define __bar_brwarw()  asm volatile (FULL_FENCE:::"memory")
0051 #define __bar_brarw()   asm volatile (ACQUIRE_FENCE:::"memory")
0052 #define __bar_bwarw()   asm volatile (".long 0x842bc000\n":::"memory")
0053 #define __bar_brwar()   asm volatile (".long 0x842dc000\n":::"memory")
0054 #define __bar_brwaw()   asm volatile (RELEASE_FENCE:::"memory")
0055 #define __bar_brar()    asm volatile (".long 0x8425c000\n":::"memory")
0056 #define __bar_brar()    asm volatile (".long 0x8425c000\n":::"memory")
0057 #define __bar_bwaw()    asm volatile (".long 0x842ac000\n":::"memory")
0058
0059 #define __smp_mb()  __bar_brwarw()
0060 #define __smp_rmb() __bar_brar()
0061 #define __smp_wmb() __bar_bwaw()
0062
0063 #define __smp_acquire_fence()   __bar_brarw()
0064 #define __smp_release_fence()   __bar_brwaw()
0065
0066 #endif /* CONFIG_SMP */
0067
0068 /*
0069  * sync:        completion barrier, all sync.xx instructions
0070  *              guarantee the last response received by bus transaction
0071  *              made by ld/st instructions before sync.s
0072  * sync.s:      inherit from sync, but also shareable to other cores
0073  * sync.i:      inherit from sync, but also flush cpu pipeline
0074  * sync.is:     the same with sync.i + sync.s
0075  */
0076 #define mb()        asm volatile ("sync\n":::"memory")
0077
0078 #ifdef CONFIG_CPU_HAS_CACHEV2
0079 /*
0080  * Using three sync.is to prevent speculative PTW
0081  */
0082 #define sync_is()   asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory")
0083 #endif
0084
0085 #include <asm-generic/barrier.h>
0086
0087 #endif /* __ASSEMBLY__ */
0088 #endif /* __ASM_CSKY_BARRIER_H */