inc/abi/entry.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __ASM_CSKY_ENTRY_H
0004 #define __ASM_CSKY_ENTRY_H
0005
0006 #include <asm/setup.h>
0007 #include <abi/regdef.h>
0008
0009 #define LSAVE_PC    8
0010 #define LSAVE_PSR   12
0011 #define LSAVE_A0    24
0012 #define LSAVE_A1    28
0013 #define LSAVE_A2    32
0014 #define LSAVE_A3    36
0015 #define LSAVE_A4    40
0016 #define LSAVE_A5    44
0017
0018 #define KSPTOUSP
0019 #define USPTOKSP
0020
0021 #define usp cr<14, 1>
0022
0023 .macro SAVE_ALL epc_inc
0024     subi    sp, 152
0025     stw tls, (sp, 0)
0026     stw lr, (sp, 4)
0027
0028     RD_MEH  lr
0029     WR_MEH  lr
0030
0031     mfcr    lr, epc
0032     movi    tls, \epc_inc
0033     add lr, tls
0034     stw lr, (sp, 8)
0035
0036     mfcr    lr, epsr
0037     stw lr, (sp, 12)
0038     btsti   lr, 31
0039     bf      1f
0040     addi    lr, sp, 152
0041     br  2f
0042 1:
0043     mfcr    lr, usp
0044 2:
0045     stw lr, (sp, 16)
0046
0047     stw     a0, (sp, 20)
0048     stw     a0, (sp, 24)
0049     stw     a1, (sp, 28)
0050     stw     a2, (sp, 32)
0051     stw     a3, (sp, 36)
0052
0053     addi    sp, 40
0054     stm r4-r13, (sp)
0055
0056     addi    sp, 40
0057     stm     r16-r30, (sp)
0058 #ifdef CONFIG_CPU_HAS_HILO
0059     mfhi    lr
0060     stw lr, (sp, 60)
0061     mflo    lr
0062     stw lr, (sp, 64)
0063     mfcr    lr, cr14
0064     stw lr, (sp, 68)
0065 #endif
0066     subi    sp, 80
0067 .endm
0068
0069 .macro  RESTORE_ALL
0070     ldw tls, (sp, 0)
0071     ldw lr, (sp, 4)
0072     ldw a0, (sp, 8)
0073     mtcr    a0, epc
0074     ldw a0, (sp, 12)
0075     mtcr    a0, epsr
0076     btsti   a0, 31
0077     ldw a0, (sp, 16)
0078     mtcr    a0, usp
0079     mtcr    a0, ss0
0080
0081 #ifdef CONFIG_CPU_HAS_HILO
0082     ldw a0, (sp, 140)
0083     mthi    a0
0084     ldw a0, (sp, 144)
0085     mtlo    a0
0086     ldw a0, (sp, 148)
0087     mtcr    a0, cr14
0088 #endif
0089
0090     ldw     a0, (sp, 24)
0091     ldw     a1, (sp, 28)
0092     ldw     a2, (sp, 32)
0093     ldw     a3, (sp, 36)
0094
0095     addi    sp, 40
0096     ldm r4-r13, (sp)
0097     addi    sp, 40
0098     ldm     r16-r30, (sp)
0099     addi    sp, 72
0100     bf  1f
0101     mfcr    sp, ss0
0102 1:
0103     rte
0104 .endm
0105
0106 .macro SAVE_REGS_FTRACE
0107     subi    sp, 152
0108     stw tls, (sp, 0)
0109     stw lr, (sp, 4)
0110
0111     mfcr    lr, psr
0112     stw lr, (sp, 12)
0113
0114     addi    lr, sp, 152
0115     stw lr, (sp, 16)
0116
0117     stw     a0, (sp, 20)
0118     stw     a0, (sp, 24)
0119     stw     a1, (sp, 28)
0120     stw     a2, (sp, 32)
0121     stw     a3, (sp, 36)
0122
0123     addi    sp, 40
0124     stm r4-r13, (sp)
0125
0126     addi    sp, 40
0127     stm     r16-r30, (sp)
0128 #ifdef CONFIG_CPU_HAS_HILO
0129     mfhi    lr
0130     stw lr, (sp, 60)
0131     mflo    lr
0132     stw lr, (sp, 64)
0133     mfcr    lr, cr14
0134     stw lr, (sp, 68)
0135 #endif
0136     subi    sp, 80
0137 .endm
0138
0139 .macro  RESTORE_REGS_FTRACE
0140     ldw tls, (sp, 0)
0141
0142 #ifdef CONFIG_CPU_HAS_HILO
0143     ldw a0, (sp, 140)
0144     mthi    a0
0145     ldw a0, (sp, 144)
0146     mtlo    a0
0147     ldw a0, (sp, 148)
0148     mtcr    a0, cr14
0149 #endif
0150
0151     ldw     a0, (sp, 24)
0152     ldw     a1, (sp, 28)
0153     ldw     a2, (sp, 32)
0154     ldw     a3, (sp, 36)
0155
0156     addi    sp, 40
0157     ldm r4-r13, (sp)
0158     addi    sp, 40
0159     ldm     r16-r30, (sp)
0160     addi    sp, 72
0161 .endm
0162
0163 .macro SAVE_SWITCH_STACK
0164     subi    sp, 64
0165     stm r4-r11, (sp)
0166     stw lr,  (sp, 32)
0167     stw r16, (sp, 36)
0168     stw r17, (sp, 40)
0169     stw r26, (sp, 44)
0170     stw r27, (sp, 48)
0171     stw r28, (sp, 52)
0172     stw r29, (sp, 56)
0173     stw r30, (sp, 60)
0174 #ifdef CONFIG_CPU_HAS_HILO
0175     subi    sp, 16
0176     mfhi    lr
0177     stw lr, (sp, 0)
0178     mflo    lr
0179     stw lr, (sp, 4)
0180     mfcr    lr, cr14
0181     stw lr, (sp, 8)
0182 #endif
0183 .endm
0184
0185 .macro RESTORE_SWITCH_STACK
0186 #ifdef CONFIG_CPU_HAS_HILO
0187     ldw lr, (sp, 0)
0188     mthi    lr
0189     ldw lr, (sp, 4)
0190     mtlo    lr
0191     ldw lr, (sp, 8)
0192     mtcr    lr, cr14
0193     addi    sp, 16
0194 #endif
0195     ldm r4-r11, (sp)
0196     ldw lr,  (sp, 32)
0197     ldw r16, (sp, 36)
0198     ldw r17, (sp, 40)
0199     ldw r26, (sp, 44)
0200     ldw r27, (sp, 48)
0201     ldw r28, (sp, 52)
0202     ldw r29, (sp, 56)
0203     ldw r30, (sp, 60)
0204     addi    sp, 64
0205 .endm
0206
0207 /* MMU registers operators. */
0208 .macro RD_MIR rx
0209     mfcr    \rx, cr<0, 15>
0210 .endm
0211
0212 .macro RD_MEH rx
0213     mfcr    \rx, cr<4, 15>
0214 .endm
0215
0216 .macro RD_MCIR rx
0217     mfcr    \rx, cr<8, 15>
0218 .endm
0219
0220 .macro RD_PGDR rx
0221     mfcr    \rx, cr<29, 15>
0222 .endm
0223
0224 .macro RD_PGDR_K rx
0225     mfcr    \rx, cr<28, 15>
0226 .endm
0227
0228 .macro WR_MEH rx
0229     mtcr    \rx, cr<4, 15>
0230 .endm
0231
0232 .macro WR_MCIR rx
0233     mtcr    \rx, cr<8, 15>
0234 .endm
0235
0236 #ifdef CONFIG_PAGE_OFFSET_80000000
0237 #define MSA_SET cr<30, 15>
0238 #define MSA_CLR cr<31, 15>
0239 #endif
0240
0241 #ifdef CONFIG_PAGE_OFFSET_A0000000
0242 #define MSA_SET cr<31, 15>
0243 #define MSA_CLR cr<30, 15>
0244 #endif
0245
0246 .macro SETUP_MMU
0247     /* Init psr and enable ee */
0248     lrw r6, DEFAULT_PSR_VALUE
0249     mtcr    r6, psr
0250     psrset  ee
0251
0252     /* Invalid I/Dcache BTB BHT */
0253     movi    r6, 7
0254     lsli    r6, 16
0255     addi    r6, (1<<4) | 3
0256     mtcr    r6, cr17
0257
0258     /* Invalid all TLB */
0259     bgeni   r6, 26
0260     mtcr    r6, cr<8, 15> /* Set MCIR */
0261
0262     /* Check MMU on/off */
0263     mfcr    r6, cr18
0264     btsti   r6, 0
0265     bt  1f
0266
0267     /* MMU off: setup mapping tlb entry */
0268     movi    r6, 0
0269     mtcr    r6, cr<6, 15> /* Set MPR with 4K page size */
0270
0271     grs r6, 1f /* Get current pa by PC */
0272     bmaski  r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
0273     andn    r6, r7
0274     mtcr    r6, cr<4, 15> /* Set MEH */
0275
0276     mov r8, r6
0277     movi    r7, 0x00000006
0278     or      r8, r7
0279     mtcr    r8, cr<2, 15> /* Set MEL0 */
0280     movi    r7, 0x00001006
0281     or      r8, r7
0282     mtcr    r8, cr<3, 15> /* Set MEL1 */
0283
0284     bgeni   r8, 28
0285     mtcr    r8, cr<8, 15> /* Set MCIR to write TLB */
0286
0287     br  2f
0288 1:
0289     /*
0290      * MMU on: use origin MSA value from bootloader
0291      *
0292      * cr<30/31, 15> MSA register format:
0293      * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0294      *   BA     Reserved  SH  WA  B   SO SEC  C   D   V
0295      */
0296     mfcr    r6, MSA_SET /* Get MSA */
0297 2:
0298     lsri    r6, 29
0299     lsli    r6, 29
0300     addi    r6, 0x1ce
0301     mtcr    r6, MSA_SET /* Set MSA */
0302
0303     movi    r6, 0
0304     mtcr    r6, MSA_CLR /* Clr MSA */
0305
0306     /* enable MMU */
0307     mfcr    r6, cr18
0308     bseti   r6, 0
0309     mtcr    r6, cr18
0310
0311     jmpi    3f /* jump to va */
0312 3:
0313 .endm
0314 #endif /* __ASM_CSKY_ENTRY_H */